LOW VOLTAGE LOW POWER FULLY DIFFERENTIAL BUFFER

2009 ◽  
Vol 18 (03) ◽  
pp. 497-502 ◽  
Author(s):  
VINCENZO STORNELLI
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Common Mode ◽  
Figures Of Merit ◽  
Fully Differential ◽  
General Performance ◽  
Rail To Rail ◽  
The Common

In this paper a useful CMOS fully-differential buffer topology is presented. The proposed solution, performing the common mode feedback operation, shows a rail-to-rail characteristic, so it is particularly suitable for low-voltage (± 0.75 V) low-power (< 400 μW) applications. The simulated results have shown excellent general performance, evaluated in terms of suitable figures of merit.

scholarly journals A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 350 ◽  
Author(s):  
Xu Bai ◽  
Jianzhong Zhao ◽  
Shi Zuo ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Serial Interface ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
28 Nm

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

scholarly journals A 0.3 V, Rail-to-Rail, Ultralow-Power, Non-Tailed, Body-Driven, Sub-Threshold Amplifier

2021 ◽  
Vol 11 (6) ◽  
pp. 2528 ◽  
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Gain Bandwidth ◽  
Common Mode ◽  
Input Stage ◽  
Fully Differential ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
Ultralow Power

A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed in this paper. The input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage. This novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered operational amplifier. A dual path compensation strategy is exploited to improve the frequency response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around 3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of 60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and mismatch variations.

scholarly journals A Low-Voltage, Ultra-Low-Power, High-Gain Operational Amplifier Design for Portable Wearable Devices

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 74
Author(s):  
Na Bai ◽  
Xiaolong Li ◽  
Yaohua Xu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Operational Amplifier ◽  
Low Voltage ◽  
Simulation Analysis ◽  
Supply Voltage ◽  
High Gain ◽  
Common Mode ◽  
Ultra Low Power ◽  
The Common

Based on the SMIC 0.13 um CMOS technology, this paper uses a 0.8 V supply voltage to design a low-voltage, ultra-low-power, high-gain, two-stage, fully differential operational amplifier. Through the simulation analysis, when the supply voltage is 0.8 V, the design circuit meets the ultra-low power consumption and also has the characteristic of high gain. The five-tube, fully differential, and common-source amplifier circuits provide the operational amplifier with high gain and large swing. Unlike the traditional common-mode feedback, this paper uses the output of the common-mode feedback as the bias voltage of the five-tube operational transconductance amplifier load, which reduces the design cost of the circuit; the structure involves self-cascoding composite MOS, which makes the common-mode feedback loop more sensitive. The frequency compensation circuit adopts Miller compensation technology with zero-pole separation, which increases the stability of the circuit. The input of the circuit uses the current mirror. A small reference current is chosen to reduce power consumption. A detailed performance simulation analysis of this operational amplifier circuit is carried out on the Cadence spectre platform. The open-loop gain of this operational amplifier is 74.1 dB, the phase margin is 61°, the output swing is 0.7 V, the common-mode rejection ratio is 109 dB, and the static power consumption is only 11.2 uW.

scholarly journals A 4-μW 0.8-V Rail-to-Rail Input/Output CMOS Fully Differential OpAmp

1970 ◽  
pp. 22
Author(s):  
M.R. Valero ◽  
S. Celma ◽  
N. Medrano
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Cmos Technology ◽  
Open Loop ◽  
Threshold Region ◽  
Input Output ◽  
Output Stage ◽  
Common Mode ◽  
Ultra Low Power ◽  
Rail To Rail

This paper presents an ultra low power rail-to-rail input/output operational amplifier (OpAmp) designed in a low cost 0.18 μm CMOS technology. In this OpAmp, rail-to-rail input operation is enabled by using complementary input pairs with gm control. To maximize the output swing a rail-to-rail output stage is employed. For low-voltage low-power operation, the operating transistors in the input and output stage are biased in the sub-threshold region. The simulated DC open loop gain is 51 dB, and the slew-rate is 0.04 V/μs with a 10 pF capacitive load connected to each of the amplifier outputs. For the same load, the simulated unity gain frequency is 131 kHz with a 64º phase margin. A common-mode feed-forward circuit (CMFF) increases CMRR, reducing drastically the variations in the output common mode voltage and keeping the DC gain almost constant. In fact, their relative error remains below 1.2 % for a (-20ºC, +120ºC) temperature span. In addition, the proposed OpAmp is very simple and consumes only 4 μW at 0.8 V supply.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Fully Differential Class-AB OTA with Improved CMRR

2017 ◽  
Vol 26 (11) ◽  
pp. 1750169 ◽  
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Gaetano Parisi ◽  
Pasquale Tommasino ◽  
Alessandro Trifiletti
Keyword(s):  
Cmos Technology ◽  
Current Mirror ◽  
Differential Mode ◽  
Common Mode ◽  
Common Mode Rejection Ratio ◽  
Class Ab ◽  
Fully Differential ◽  
Rejection Ratio ◽  
Mode Behavior ◽  
The Common

This paper presents a fully differential class-AB current mirror OTA that improves the common-mode behavior of a topology that presents very good differential-mode performance but poor common-mode rejection ratio (CMRR). The proposed solution requires a low-current auxiliary circuit driven by the input signal, to compensate the effect of the common-mode input component. Simulations in 40-nm CMOS technology show a net reduction of common-mode gain of more than 90[Formula: see text]dB without affecting the differential-mode behavior; a sample-and-hold amplifier exploiting the proposed amplifier has also been simulated.

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