A Low-Power Quadrature LC–Oscillator using Core-and-Coupling Current-Reuse

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

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The S- and C- band Low-power CMOS LNA Using the Current-reuse Technique

2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus) ◽

10.1109/elconrus51938.2021.9396727 ◽

2021 ◽

Author(s):

Roman Yu. Musenov ◽

Elena S. Yanakova

Keyword(s):

Low Power ◽

Current Reuse ◽

Low Power Cmos ◽

Cmos Lna

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A low power quadrature class D LC oscillator with 0.4V supply

2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) ◽

10.1109/mixdes.2014.6872169 ◽

2014 ◽

Author(s):

Andre Bispo ◽

Filipe Quendera ◽

Ricardo Madeira ◽

Joao P. Oliveira ◽

Luis B. Oliveira

Keyword(s):

Low Power ◽

Lc Oscillator ◽

Class D

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A Very Low Power Quadrature VCO with Modified Current-Reuse and Back-Gate Coupling Topology

Journal of Circuits System and Computers ◽

10.1142/s0218126617501845 ◽

2017 ◽

Vol 26 (11) ◽

pp. 1750184 ◽

Cited By ~ 8

Author(s):

Qiuzhen Wan ◽

Jun Dong ◽

Hui Zhou ◽

Fei Yu

Keyword(s):

Power Consumption ◽

Low Power ◽

Phase Noise ◽

Tuning Range ◽

Supply Voltage ◽

Voltage Controlled Oscillator ◽

Back Gate ◽

Current Reuse ◽

Quadrature Vco ◽

In Series

In this paper, a very low power modified current-reused quadrature voltage-controlled oscillator (QVCO) is proposed with the back-gate coupling technique for the quadrature signal generation. By stacking switching transistors in series like a cascode, the modified current-reused QVCO can be constructed in a totem-pole manner to reuse the dc biasing current and lower the power consumption. By utilizing the back-gates of switching transistors as coupling terminals to achieve the quadrature outputs, the back-gate coupled QVCO improves the phase noise and reduces the power consumption compared to the conventional coupling transistor based topology. Together with the modified current-reuse and back-gate coupling techniques, the proposed QVCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of low phase noise and wide tuning range. With a dc power of 1.6[Formula: see text]mW under a 0.8[Formula: see text]V supply voltage, the simulation results show the tuning range of the QVCO is from 2.36 to 3.04[Formula: see text]GHz as the tuning voltage is varied from 0.8 to 0.0[Formula: see text]V. The phase noise is [Formula: see text]118.3[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset frequency from the carrier frequency of 2.36[Formula: see text]GHz and the corresponding figure-of-merit of the QVCO is [Formula: see text]183.7[Formula: see text]dBc/Hz.

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Review on 60GHz Low Noise Amplifier for Low Power and Linearity

Advances in Wireless Technologies and Telecommunication - Handbook of Research on Advanced Trends in Microwave and Communication Engineering ◽

10.4018/978-1-5225-0773-4.ch009 ◽

2017 ◽

pp. 283-315

Author(s):

Siva Sankar Yellampalli ◽

Rashmi S. B.

Keyword(s):

Low Power ◽

Power Dissipation ◽

Radio Spectrum ◽

Low Noise ◽

Bias Current ◽

60 Ghz ◽

Current Reuse ◽

Extremely High Frequency ◽

Noise Amplifier ◽

Circuit Components

In the extremely high frequency radio spectrum of 30-300 GHz, the band from 57-64 GHz has been de-regulated. The biggest challenge in designing products at this frequency is the design of CMOS based transceiver circuit components. This chapter deals with the review of 60 GHz LNA design. LNA was chosen as this is the first component of the receiver circuit and its performance affects the transceiver efficiency. In this chapter the review is done on 60GHz LNA's design addressing the linearization, and low power challenges. To address these challenges, in literature there are many LNA architectures such as simple cascode topology, Current reuse topology etc. The major advantage of current reuse topology is its load transistor shares the same bias current of driver which results in reduced power dissipation by maintaining the maximum gain. The main objective of this chapter is to address gain, power dissipation and linearization challenges by reviewing the different current reuse architectures and linearization techniques used to implement 60GHz LNA.

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