Miniaturized millimeter-wave on-chip bandpass filter design in 0.13-μm SiGe BiCMOS technology

Author(s):  
Zhang Ju Hou ◽  
Quan Xue ◽  
Yang Yang ◽  
Xi Zhu ◽  
Eryk Dutkiewicz
IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 178976-178990
Author(s):  
Federico Alimenti ◽  
Guendalina Simoncini ◽  
Gianluca Brozzetti ◽  
Daniele Dal Maistro ◽  
Marc Tiebout

Author(s):  
Yang Chen ◽  
Zhaoyang Qiu ◽  
Xiaofei Di ◽  
Xianqing Chen ◽  
Yu-Dong Zhang

This paper presents the analytical resistance–capacitance–inductance–conductance (RLCG) model of the on-chip interconnect line (IL) based on its structure, and the proposed model can be used to design IL and analyze the delay characteristics. Using electromagnetic (EM) simulation, the relations between the inductance, quality factor and the width, length of IL are obtained, which verifies the proposed RLCG model of IL. The delay model of IL is derived and verified with respect to the effects of the [Formula: see text] and [Formula: see text] by simulation, which can provide the benefit for the true-time delay line (TTDL) design using IL. This work proposes the experiments on the delay characteristics of 3-bit TTDL with IL based on 0.13[Formula: see text][Formula: see text]m SiGe BiCMOS technology. The group delay and transient delay of the TTDL are measured, which exhibits a maximal relative delay of 35 ps with an average of 5 ps delay resolution over a frequency range of 14–34[Formula: see text]GHz. The results are consistent with the delay analysis based on the proposed IL model.


Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1608
Author(s):  
Kai Men ◽  
Hang Liu ◽  
Kiat Seng Yeo

In this work, the design of a novel Ka-band miniaturized bandpass filter with broad bandwidth is demonstrated by using inversely coupled U-shaped transmission lines. In the proposed filter, two transmission zeros can be generated within a cascaded U-shaped structure and it can also be proven that, by inversely coupling two stacked U-shaped transmission lines, the notch frequency at the upper stopband can be shifted to a lower frequency, which results in a smaller chip size. The key parameters affecting the performance of the proposed filter are investigated in detail with the effective lumped-element circuit illustrated. Fabricated in a 0.13-μm SiGe BiCMOS process, the proposed filter achieves an insertion loss of 3.6 dB at a frequency of 28.75 GHz and the measured bandwidth is from 20.75 GHz to 41 GHz. The return loss is better than −10 dB from 20.5 GHz to 39 GHz. The lower transmission zero is located at 11.75 GHz with a suppression of 54 dB while the upper transmission zero is around 67 GHz with an attenuation of 34.6 dB. The measurement agrees very well with the simulation results and the overall chip size of the proposed filter is 176 × 269 μm2.


2016 ◽  
Vol 8 (4-5) ◽  
pp. 703-712
Author(s):  
Xin Yang ◽  
Xiao Xu ◽  
Takayuki Shibata ◽  
Toshihiko Yoshimasu

In this paper, a W-band (80 GHz) sub-harmonic mixer (SHM) IC is designed, fabricated and measured in 130-nm SiGe BiCMOS technology. The presented SHM IC makes use of a common emitter common collector transistor pair structure with a bottom-LO-configuration to decrease the LO power requirement and a tail current source to flatten the conversion gain. On-chip Marchand balun is designed for W-band on-wafer measurements. The SHM IC presented in this paper has exhibited a conversion gain of 3.9 dB at 80 GHz RF signal with an LO power of only −7 dBm at 39.5 GHz. The mixer core consumes only 0.68 mA at a supply voltage of 3.3 V.


2011 ◽  
Vol 58 (7) ◽  
pp. 1837-1845 ◽  
Author(s):  
Huey-Ru Chuang ◽  
Lung-Kai Yeh ◽  
Pei-Chun Kuo ◽  
Kai-Hsiang Tsai ◽  
Han-Lin Yue

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