Power consumption trade-off between power amplifier OBO, DPD, and clipping and filtering

Author(s):  
Sandrine Boumard ◽  
Mika Lasanen ◽  
Olli Apilo ◽  
Atso Hekkala ◽  
Cedric Cassan ◽  
...  
2021 ◽  
Vol 17 (2) ◽  
pp. 1-25
Author(s):  
Dat Tran ◽  
Christof Teuscher

Emerging memcapacitive nanoscale devices have the potential to perform computations in new ways. In this article, we systematically study, to the best of our knowledge for the first time, the computational capacity of complex memcapacitive networks, which function as reservoirs in reservoir computing, one of the brain-inspired computing architectures. Memcapacitive networks are composed of memcapacitive devices randomly connected through nanowires. Previous studies have shown that both regular and random reservoirs provide sufficient dynamics to perform simple tasks. How do complex memcapacitive networks illustrate their computational capability, and what are the topological structures of memcapacitive networks that solve complex tasks with efficiency? Studies show that small-world power-law (SWPL) networks offer an ideal trade-off between the communication properties and the wiring cost of networks. In this study, we illustrate the computing nature of SWPL memcapacitive reservoirs by exploring the two essential properties: fading memory and linear separation through measurements of kernel quality. Compared to ideal reservoirs, nanowire memcapacitive reservoirs had a better dynamic response and improved their performance by 4.67% on three tasks: MNIST, Isolated Spoken Digits, and CIFAR-10. On the same three tasks, compared to memristive reservoirs, nanowire memcapacitive reservoirs achieved comparable performance with much less power, on average, about 99× , 17×, and 277×, respectively. Simulation results of the topological transformation of memcapacitive networks reveal that that topological structures of the memcapacitive SWPL reservoirs did not affect their performance but significantly contributed to the wiring cost and the power consumption of the systems. The minimum trade-off between the wiring cost and the power consumption occurred at different network settings of α and β : 4.5 and 0.61 for Biolek reservoirs, 2.7 and 1.0 for Mohamed reservoirs, and 3.0 and 1.0 for Najem reservoirs. The results of our research illustrate the computational capacity of complex memcapacitive networks as reservoirs in reservoir computing. Such memcapacitive networks with an SWPL topology are energy-efficient systems that are suitable for low-power applications such as mobile devices and the Internet of Things.


2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Premmilaah Gunasegaran ◽  
Jagadheswaran Rajendran ◽  
Selvakumar Mariappan ◽  
Yusman Mohd Yusof ◽  
Zulfiqar Ali Abdul Aziz ◽  
...  

Purpose The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA). Design/methodology/approach The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability. Findings With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation. Practical implications The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design. Originality/value The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.


2014 ◽  
Vol 24 (8) ◽  
pp. 551-553 ◽  
Author(s):  
Jongwon Lee ◽  
Jooseok Lee ◽  
Kyounghoon Yang

2016 ◽  
Vol 4 (4) ◽  
pp. 118-121
Author(s):  
Pankaj Prajapati ◽  
Dr. Shyam Akashe

In the beginning of the last decade, battery-powered hand-held devices such as mobile phones and laptop computers emerged. For that application we have to design a device which will consume minimum amount of energy. For that reason in this article we focused on power consumption and how to calculate the power. In this paper, an analysis of different delay lines based on CMOS architecture has been done. The effect of supply voltage on digital delay lines has been analysed as how supply voltage affected the value of power consumption of the digital delay line. After the analysis of those performance parameters, the trade-off has been made for better performance of delay lines.


2017 ◽  
Vol 26 (10) ◽  
pp. 1750162
Author(s):  
Atefeh Salimi ◽  
Rasoul Dehghani ◽  
Abdolreza Nabavi

A novel envelope modulator for envelope tracking RF power amplifier (PA) is presented in this paper. The proposed modulator consists of a parallel combination of analog class AB and digitally controlled hybrid PAs. The analog and digital class AB PAs are effective in both reducing the clock frequency and also static power dissipation, thus improving the efficiency of the modulator. On the other hand, lower clock frequencies result in simpler and more power-efficient digital to analog converters required in the architecture. The modulator digital block is evaluated with a 45[Formula: see text]nm CMOS technology. The overall power consumption of the digital block is around 76[Formula: see text]mW at 800[Formula: see text]MHz clock frequency. As an application, the designed digital block is incorporated in a complete envelope modulator architecture. The overall efficiency of the modulator, including the digital block power consumption, is around 80.7% at an average 32[Formula: see text]dBm output power for a 5[Formula: see text]MHz input signal.


Author(s):  
C Pinatel ◽  
S Vuye ◽  
M. Riet ◽  
C Dubon-Chevalier ◽  
B Rojat ◽  
...  

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