Enhancing Hot-Carrier Reliability of Dual-Gate Low-Temperature Polysilicon TFTs by Increasing Lightly Doped Drain Length

2020 ◽  
Vol 41 (10) ◽  
pp. 1524-1527
Author(s):  
Jian-Jie Chen ◽  
Ting-Chang Chang ◽  
Hong-Chih Chen ◽  
Kuan-Ju Zhou ◽  
Chuan-Wei Kuo ◽  
...  
Keyword(s):  
Low Temperature ◽  
Hot Carrier ◽  
Dual Gate ◽  
Lightly Doped Drain

Highly-Doped Region Optimization for Reduced Hot-Carrier Effects in Dual-Gate Low Temperature Polysilicon TFTs

2021 ◽  
pp. 1-1
Author(s):  
Jian-Jie Chen ◽  
Po-Hsun Chen ◽  
Ting-Chang Chang ◽  
Yu-Fa Tu ◽  
Kuan-Ju Zhou ◽  
...  
Keyword(s):  
Low Temperature ◽  
Hot Carrier ◽  
Dual Gate ◽  
Hot Carrier Effects

Inhibiting the Kink Effect and Hot-Carrier Stress Degradation Using Dual-Gate Low-Temperature Poly-Si TFTs

2020 ◽  
Vol 41 (1) ◽  
pp. 54-57 ◽  
Author(s):  
Hong-Chih Chen ◽  
Hong-Yi Tu ◽  
Hui-Chun Huang ◽  
Wei-Chih Lai ◽  
Ting-Chang Chang ◽  
...  
Keyword(s):  
Low Temperature ◽  
Hot Carrier ◽  
Kink Effect ◽  
Hot Carrier Stress ◽  
Stress Degradation ◽  
Dual Gate

Analysis of Hot Carrier Effect in Low-Temperature Poly-Si Gate-Overlapped Lightly Doped Drain Thin Film Transistors

2003 ◽  
Vol 42 (Part 1, No. 6A) ◽  
pp. 3354-3360 ◽  
Author(s):  
Tetsuo Kawakita ◽  
Hidehiro Nakagawa ◽  
Yukiharu Uraoka ◽  
Takashi Fuyuki
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Thin Film Transistors ◽  
Hot Carrier ◽  
Carrier Effect ◽  
Hot Carrier Effect ◽  
Lightly Doped Drain

Hot-carrier reliability in double-implanted lightly doped drain devices for advanced drams

1992 ◽  
Vol 28 (1) ◽  
pp. 19-21 ◽  
Author(s):  
A. Ditali ◽  
P. Fazan ◽  
I. Khan
Keyword(s):  
Hot Carrier ◽  
Lightly Doped Drain

Dual-gate nanostructured silicon MOSFETs: fabrication and low temperature characterization

1993 ◽  
Vol 21 (1-4) ◽  
pp. 405-408 ◽  
Author(s):  
C. de Graaf ◽  
J. Caro ◽  
K. Heyers ◽  
S. Radelaar
Keyword(s):  
Low Temperature ◽  
Nanostructured Silicon ◽  
Dual Gate

An Asymmetric Dual Gate Poly-Si TFTs for Improving Hot Carrier Stress Stability and Kink Effect Suppression

2006 ◽  
Vol 910 ◽  
Author(s):  
Joong Hyun Park ◽  
Woo Jin Nam ◽  
Jae Hoon Lee ◽  
Min Koo Han
Keyword(s):  
Current Flow ◽  
Total Current ◽  
Hot Carrier ◽  
Kink Effect ◽  
Gate Structure ◽  
Hot Carrier Stress ◽  
Dual Gate ◽  
Drain Bias ◽  
Current Operation ◽  
Si Thin Film

AbstractAn asymmetric dual gate poly-Si thin film transistors (TFTs), which is consist a long-gate TFT and a short-gate TFT, were fabricated in order to suppress the kink current and increase the reliability. The long-gate TFT operates in a linear regime and limits the total current flow by its current operation region. The asymmetric dual-gate does not exhibit from the kink current in a high drain bias due to the distribution of lateral electric field. The asymmetric dual-gate structure improves kink-free characteristics compared with conventional single and dual-gate TFTs. The hot-carrier stress reliability is successfully improved due to kink current suppression.

Gate Overlapped Lightly Doped Drain Poly-Si TFTs Employing 45° Tilt Implant For Source and Drain

2004 ◽  
Vol 808 ◽  
Author(s):  
Jae-Hoon Lee ◽  
Moon-Young Shin ◽  
Heesun Shin ◽  
Woo-Jin Nam ◽  
Min-Koo Han
Keyword(s):  
Leakage Current ◽  
Short Channel ◽  
Hot Carrier ◽  
Ion Doping ◽  
Channel Gate ◽  
Hot Carrier Stress ◽  
Lightly Doped Drain

ABSTRACTWe propose a short channel gate overlapped lightly doped drain (GOLDD) poly-Si TFT employing 45° tilt implant for source and drain (S/D) regions without any additional ion doping or mask. Oblique-incident ELA activation is performed to activate both n+ S/D and n- LDD regions as well as cure junction defects. The proposed poly-Si TFT can suppress the anomalous leakage current, and exhibit the better reliability against the hot-carrier stress.

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