Improvement Design for Turn-On Switching Characteristics in Surface Buffer Insulated Gate Bipolar Transistor

2020 ◽  
Vol 41 (12) ◽  
pp. 1814-1816
Author(s):  
Wataru Saito ◽  
Shin-Ichi Nishizawa
2015 ◽  
Vol 54 (4S) ◽  
pp. 04DP11 ◽  
Author(s):  
Iliya Pesic ◽  
Dondee Navarro ◽  
Masato Fujinaga ◽  
Yoshiharu Furui ◽  
Mitiko Miura-Mattausch

2021 ◽  
Author(s):  
Hongming Ma ◽  
Wenyuan Zhang ◽  
Yan Wang

Abstract A 10kV-level silicon carbide (SiC) insulated gate bipolar transistor (IGBT) with field limiting rings (FLRs) is designed and simulated with Sentaurus TCAD, the detailed optimization method and comparisons are presented in this paper. Linearly varying spacing between rings is introduced to SiC IGBT and adjustment is performed on width of rings, the final structure achieves a breakdown voltage over 12kV with a termination length of 164.5 µm , which is 69.93% lower than that of conventional structure with a fixed ring spacing. Moreover, the final design can decrease the sensitivity to the interface charges, the tolerance to positive surface charges exceeds 8 × 10 11 cm − 2 , which is 3.5 times that of the conventional structure. Besides, double pulse measurements prove no degradation of conduction and switching characteristics.


2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.


2012 ◽  
Vol 33 (12) ◽  
pp. 1684-1686 ◽  
Author(s):  
Huaping Jiang ◽  
Jin Wei ◽  
Bo Zhang ◽  
Wanjun Chen ◽  
Ming Qiao ◽  
...  

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