Low chip area, low power dissipation, programmable, current mode, 10-bits, SAR ADC implemented in the CMOS 130nm technology

2015 ◽  
Author(s):  
Rafal Dlugosz ◽  
Gunter Fischer
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Current Mode ◽  
Sar Adc ◽  
Chip Area ◽  
Low Power Dissipation

IMPROVED DYNAMIC CURRENT MODE LOGIC FOR LOW POWER APPLICATIONS

2008 ◽  
Vol 17 (02) ◽  
pp. 183-190 ◽  
Author(s):  
S. RAMAKRISHNAN ◽  
K. T. LAU
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Power Dissipation ◽  
Current Mode ◽  
Total Power ◽  
Active Mode ◽  
Dynamic Power ◽  
Current Mode Logic ◽  
Low Power Dissipation ◽  
Standby Mode

In this paper, a newly improved dynamic current mode logic (I-DyCML) is proposed to achieve low power dissipation. The principle used in I-DyCML is the reduction of the leakage current by turning the part of the circuit to "standby mode", when not in use, while achieving lower dynamic power during the active mode. HSpice simulations show that I-DyCML saves up to 15–30% of the total power dissipation when compared to Dynamic Current mode logic.

A Fully-Integrated D-Band Frequency Synthesizer in 0.13-μm SiGe BiCMOS

2015 ◽  
Vol 25 (01) ◽  
pp. 1640010
Author(s):  
Jin He ◽  
Yong-Zhong Xiong ◽  
Jiankang Li ◽  
Muthukumaraswamy Annamalai Arasu ◽  
Yue Ping Zhang
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Frequency Synthesizer ◽  
Frequency Multiplier ◽  
Band Frequency ◽  
Chip Area ◽  
Fully Integrated ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Low Power Dissipation

This paper presents a fully-integrated D-band frequency synthesizer (FS) in 0.13-[Formula: see text]m SiGe BiCMOS technology. The proposed FS consists of a 20-GHz phase-locked loop (PLL) and a frequency multiplier including a doubler ([Formula: see text][Formula: see text]2) and a quadrupler ([Formula: see text][Formula: see text]4). The FS generates the D-band output signals from 164.08 to 166.19[Formula: see text]GHz. At 166.19[Formula: see text]GHz, the measured phase noises (PN) at 100-kHz and 1-MHz offset frequencies are [Formula: see text]54.07[Formula: see text]dBc/Hz and [Formula: see text]72.29[Formula: see text]dBc/Hz, respectively. The proposed FS achieves the low power dissipation of around 110[Formula: see text]mW and the chip area is [Formula: see text] including all testing pads. The FS has great potential to be used for low-power D-band applications.

Low Power dissipation of Ring Counter using Dual sleep Transistor approach

2014 ◽  
Vol 4 (3) ◽  
pp. 9-13
Author(s):  
M. Balaji ◽  
◽  
B. Keerthana ◽  
K. Varun ◽  
◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Ring Counter ◽  
Low Power Dissipation

scholarly journals Low-Power Dissipation 1060-nm VCSELs for Optical Interconnect

2015 ◽  
Vol 43 (7) ◽  
pp. 430
Author(s):  
Tomofumi KISE ◽  
Hitoshi SHIMIZU ◽  
Hideyuki NASU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Optical Interconnect ◽  
Low Power Dissipation

Low Power Dissipation 980 nm Single Mode Pumping Source Laser with Wavelength Stabilization

2016 ◽  
Vol 37 (1) ◽  
pp. 33-37
Author(s):  
李辉 LI Hui ◽  
都继瑶 DU Ji-yao ◽  
曲轶 QU Yi ◽  
张晶 ZHANG Jing ◽  
李再金 LI Zai-jin ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Single Mode ◽  
Wavelength Stabilization ◽  
Low Power Dissipation

A Direct Bulk Coupling PMOS Colpitts QVCO Using Capacitive-Feedback Structure

2019 ◽  
Vol 28 (08) ◽  
pp. 1950125
Author(s):  
Jianqun Ding ◽  
Lijun Huang ◽  
Xianwu Mi ◽  
Dajiang He ◽  
Shenghai Chen ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Figure Of Merit ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Low Power Dissipation ◽  
Feedback Structure ◽  
Voltage Swing ◽  
Low Supply Voltage ◽  
Capacitive Feedback

In this paper, a full PMOS Colpitts quadrature voltage-controlled oscillator (QVCO) topology, suitable for low supply voltage and low power dissipation, is presented. For an enhanced voltage swing under a low supply voltage, the capacitive-feedback technique is employed. Quadrature coupling is achieved by employing direct bulk coupling technique, leading to reduction in both power and chip area. The proposed QVCO covers a 5% tuning range between 2.325 GHz and 2.435 GHz, and the phase noise is [Formula: see text]128.2 dBc/Hz at 1-MHz offset from the 2.34-GHz carrier while consuming only 0.535 mW from 0.55-V supply voltage, yielding a figure-of-merit (FoM) of 198 dBc/Hz.

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