IMPROVED DYNAMIC CURRENT MODE LOGIC FOR LOW POWER APPLICATIONS

In this paper, a newly improved dynamic current mode logic (I-DyCML) is proposed to achieve low power dissipation. The principle used in I-DyCML is the reduction of the leakage current by turning the part of the circuit to "standby mode", when not in use, while achieving lower dynamic power during the active mode. HSpice simulations show that I-DyCML saves up to 15–30% of the total power dissipation when compared to Dynamic Current mode logic.

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Low Power Built-In Self-Test Schemes for Array and Booth Multipliers

VLSI Design ◽

10.1155/2001/67893 ◽

2001 ◽

Vol 12 (3) ◽

pp. 431-448 ◽

Cited By ~ 1

Author(s):

D. Bakalist ◽

X. Kavousianos ◽

H. T. Vergos ◽

D. Nikolos ◽

G. Ph. Alexiou

Keyword(s):

Low Power ◽

Power Dissipation ◽

Average Power ◽

Total Power ◽

Power Efficient ◽

Test Application ◽

Low Power Dissipation ◽

Recent Trends ◽

Self Test ◽

Built In Self Test

Recent trends in IC technology have given rise to a new requirement, that of low power dissipation during testing, that Built-In Self-Test (BIST) structures must target along with the traditional requirements. To this end, by exploiting the inherent properties of Carry Save, Carry Propagate and modified Booth multipliers, in this paper we propose new power-efficient BIST structures for them. The proposed BIST schemes are derived by: (a) properly assigning the Test Pattern Generator (TPG) outputs to the multiplier inputs, (b) modifying the TPG circuits and (c) reducing the test set length. Our results indicate that the total power dissipated during testing can be reduced from 29.3% to 54.9%, while the average power per test vector applied can be reduced from 5.8% to 36.5% and the peak power dissipation can be reduced from 15.5% to 50.2% depending on the implementation of the basic cells and the size of the multiplier. The test application time is also significantly reduced, while the introduced BIST schemes implementation area is small.

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Low chip area, low power dissipation, programmable, current mode, 10-bits, SAR ADC implemented in the CMOS 130nm technology

2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES) ◽

10.1109/mixdes.2015.7208541 ◽

2015 ◽

Cited By ~ 4

Author(s):

Rafal Dlugosz ◽

Gunter Fischer

Keyword(s):

Low Power ◽

Power Dissipation ◽

Current Mode ◽

Sar Adc ◽

Chip Area ◽

Low Power Dissipation

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LOW POWER VLSI TECHNIQUES FOR PORTABLE DEVICES

International Journal of Engineering Technologies and Management Research ◽

10.29121/ijetmr.v5.i2.2018.648 ◽

2020 ◽

Vol 5 (2) ◽

pp. 223-232

Author(s):

Sandeep Singh ◽

Neeraj Gupta ◽

Rashmi Gupta

Keyword(s):

Low Power ◽

Leakage Current ◽

Power Dissipation ◽

Low Power Design ◽

Vital Role ◽

Vlsi Circuits ◽

Portable Devices ◽

Design Strategies ◽

Power Devices ◽

Dynamic Power

In the present day scenario, designing a circuit with low power has become very important and challenging task. The designing of any processor for portable devices demands low power. This can be achieved by incorporating low power design strategies and rules at various stages of design. To increase the performance of portable devices, the power backup should be taken in consideration, which is extremely desirable from the users prospective. As we approaches towards the sub-micron technology the requirement of low power devices increases significantly. But at the same time leakage current and dynamic power dissipation play a vital role to diminish the performance of portable devices. This paper presents techniques to reduce the power dissipation and various methodologies to increase the speed of device. That is very beneficial for designing of future VLSI circuits.

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Realization of Various Topologies of Adders Based on H-Dycml

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.f4592.049620 ◽

2020 ◽

Vol 9 (4) ◽

pp. 1865-1891

Keyword(s):

Low Power ◽

Power Dissipation ◽

High Speed ◽

Current Mode ◽

Cmos Technology ◽

Performance Parameters ◽

Current Mode Logic ◽

Look Ahead ◽

Overall Performance ◽

Power Delay Product

Power consumption minimization in a circuit becomes imperative with growth in demands of portable goods. However, at the same time, its speed limits the performance of a system. Therefore, there is a need of choosing optimum circuit architecture that takes into account the both conflicting parameters, that is, power dissipation and speed. Arithmetic unit is one of the vital components of portable goods and out of all arithmetic operations, adders are the most commonly used. To address the issue of high power dissipation, low-power designing styles are becoming prominent now-a-days. Hybrid Dynamic Current Mode Logic is high-speed, low-power designing style that has been recently proposed in literature. Therefore, this paper presents the comparison between performances of various topologies of adders that are implemented using a high-speed, low-power designing style: Hybrid-Dynamic Current Mode Logic (H-DyCML). All the circuits are realized in Cadence Virtuoso using 180nm CMOS technology parameter. Various performance parameters are evaluated such as: Delay, Power, Power-Delay Product, and hardware utilization. It is found that carry look-ahead adder out-stands other adders in terms of overall performance.

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