A Fully-Integrated D-Band Frequency Synthesizer in 0.13-μm SiGe BiCMOS

This paper presents a fully-integrated D-band frequency synthesizer (FS) in 0.13-[Formula: see text]m SiGe BiCMOS technology. The proposed FS consists of a 20-GHz phase-locked loop (PLL) and a frequency multiplier including a doubler ([Formula: see text][Formula: see text]2) and a quadrupler ([Formula: see text][Formula: see text]4). The FS generates the D-band output signals from 164.08 to 166.19[Formula: see text]GHz. At 166.19[Formula: see text]GHz, the measured phase noises (PN) at 100-kHz and 1-MHz offset frequencies are [Formula: see text]54.07[Formula: see text]dBc/Hz and [Formula: see text]72.29[Formula: see text]dBc/Hz, respectively. The proposed FS achieves the low power dissipation of around 110[Formula: see text]mW and the chip area is [Formula: see text] including all testing pads. The FS has great potential to be used for low-power D-band applications.

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Low Voltage Low Power Fully Integrated Chaos Generator

Journal of Circuits System and Computers ◽

10.1142/s0218126618501554 ◽

2018 ◽

Vol 27 (10) ◽

pp. 1850155 ◽

Cited By ~ 10

Author(s):

Jie Jin ◽

LV Zhao

Keyword(s):

Low Power ◽

Power Dissipation ◽

Low Voltage ◽

Supply Voltage ◽

Electronic Components ◽

Ic Design ◽

Chip Area ◽

Fully Integrated ◽

Chaos Generator ◽

Wide Range

A low voltage low power fully integrated chaos generator is presented in this paper. Comparing with the conventional off-the-shelf electronic components-based chaos generators, the designed circuit is fully integrated, and it achieves lower supply voltage, lower power dissipation and smaller chip area. The proposed fully integrated chaos generator is verified with GlobalFoundries 0.18[Formula: see text][Formula: see text]m CMOS 1P6M RF process using Cadence IC Design Tools. The simulation results demonstrate that the fully integrated chaos generator consumes only 17[Formula: see text]mW from [Formula: see text]2.5[Formula: see text]V supply voltage. Moreover, the chip area of the chaos generator is only 1.755[Formula: see text]mm2 including the testing pads, and it has a wide range of practical application prospects.

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Low chip area, low power dissipation, programmable, current mode, 10-bits, SAR ADC implemented in the CMOS 130nm technology

2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES) ◽

10.1109/mixdes.2015.7208541 ◽

2015 ◽

Cited By ~ 4

Author(s):

Rafal Dlugosz ◽

Gunter Fischer

Keyword(s):

Low Power ◽

Power Dissipation ◽

Current Mode ◽

Sar Adc ◽

Chip Area ◽

Low Power Dissipation

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A fully integrated low-power K-band chem-bio-sensor with on-chip DC read-out in SiGe BiCMOS technology

2016 46th European Microwave Conference (EuMC) ◽

10.1109/eumc.2016.7824331 ◽

2016 ◽

Cited By ~ 1

Author(s):

F. I. Jamal ◽

S. Guha ◽

M. H. Eissa ◽

C. Meliani ◽

H. J. Ng ◽

...

Keyword(s):

Low Power ◽

Fully Integrated ◽

Bicmos Technology ◽

Sige Bicmos ◽

On Chip ◽

K Band

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An Area-Efficient and Programmable 4 × 25-to-28.9 Gb/s Optical Receiver with DCOC in 0.13 µm SiGe BiCMOS

Electronics ◽

10.3390/electronics9061032 ◽

2020 ◽

Vol 9 (6) ◽

pp. 1032

Author(s):

Haojie Xu ◽

Jiarui Liu ◽

Zhiyu Wang ◽

Min Zhou ◽

Jiongjiong Mo ◽

...

Keyword(s):

Low Power ◽

Current Source ◽

Optimization Method ◽

Optical Receiver ◽

Chip Area ◽

Offset Cancellation ◽

Noise Optimization ◽

Bicmos Technology ◽

Sige Bicmos ◽

Area Efficient

In this paper, we present an area-efficient noise-optimized programmable 4 × 25-to-28.9 Gb/s optical receiver. Both high- and low-power modes are available for the receiver to meet different requirements. Emitter degeneration provides the input transimpedance amplifier (TIA) stage with improved stability. The noise of the TIA with emitter degeneration is analyzed, and an improved noise optimization method for the TIA is proposed. A sink current source with emitter degeneration in a DC offset cancellation (DCOC) loop reduces the noise introduced by the DCOC circuit. Moreover, with parasitic capacitor utilization in the DCOC loop and capacitive emitter degeneration in the variable-gain amplifier (VGA) stage, the chip area is minimized. Fabricated in a 0.13 µm SiGe BiCMOS technology, the receiver achieved a small area of 0.54 mm2 per lane. The measured bit error rate (BER) is 10−12 with input signal varying from 110 μApp to 1150 μApp. The one-lane power dissipation values in the low-power and high-power modes are 84.97 mW and 123.75 mW, respectively.

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