A power-efficient polyphase sharpened CIC filter for sigma-delta ADCs

2011 ◽  
Author(s):  
Nikhil Reddy Karnati ◽  
Kye-Shin Lee ◽  
Joan Carletta ◽  
Robert Veillette
Keyword(s):  
Sigma Delta ◽  
Power Efficient ◽  
Cic Filter

scholarly journals A Sigma-Delta ADC for Signal Conditioning IC of Automotive Piezo-Resistive Pressure Sensors with over 80 dB SNR

Sensors ◽  
2018 ◽  
Vol 18 (12) ◽  
pp. 4199 ◽  
Author(s):  
Behnam Samadpoor Rikan ◽  
Sang-Yun Kim ◽  
Nabeel Ahmad ◽  
Hamed Abbasizadeh ◽  
Muhammad Riaz Ur Rehman ◽  
...  
Keyword(s):  
Input Signal ◽  
Flicker Noise ◽  
Signal To Noise Ratio ◽  
Pressure Sensors ◽  
High Gain ◽  
Cmos Process ◽  
Signal Conditioning ◽  
Sigma Delta ◽  
Cic Filter ◽  
Decimation Filter

This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm2 where the area of the decimation filter is only 0.075 mm2. For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.

A Power-Efficient Tunable Narrow-Band Digital Front End for Bandpass Sigma–Delta ADCs in Digital FM Receivers

2010 ◽  
Vol 57 (11) ◽  
pp. 883-887 ◽  
Author(s):  
Ahmed Shahein ◽  
Mohamed Afifi ◽  
Markus Becker ◽  
Niklas Lotze ◽  
Yiannos Manoli
Keyword(s):  
Narrow Band ◽  
Sigma Delta ◽  
Power Efficient ◽  
Front End

Design of a Digital Decimation Filter for High-Precision 4-Order Sigma-Delta ADC

2012 ◽  
Vol 503 ◽  
pp. 415-419 ◽  
Author(s):  
Wei Ping Chen ◽  
Qiang Fu ◽  
Xiao Wei Liu ◽  
Yan Xiao ◽  
Bin Zhang ◽  
...  
Keyword(s):  
High Precision ◽  
Sampling Rate ◽  
Stop Band ◽  
Cutoff Frequency ◽  
Pass Band ◽  
Sigma Delta ◽  
Band Filter ◽  
Cic Filter ◽  
Decimation Filter ◽  
Sigma Delta Adc

In this paper, a design of a digital decimation filter which has a output of 24 bits for high-precision 4-ordes Σ-Δ ADC is proposed. The digital decimation filter includes a CIC filter, a compensation filter and a half band filter. The over-sampling rate of the digital decimation filter is 256, the cutoff frequency is 1kHz, the coefficient of the pass-band ripple is -0.25dB, the stop-band attenuation is -162dB, simulation results using Matlab and modelsim are correct, the result of the FPGA verification shows that the design meet the requirement of the high-precision 4-ordes Σ-Δ ADC.

Single-loop sigma delta modulator design and verification for cognitive IoT applications

2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Vamsee Krishna S. ◽  
Sudhakara Reddy P. ◽  
Chandra Mohan Reddy S.
Keyword(s):  
Discrete Time ◽  
Noise Shaping ◽  
Third Order ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Content Type ◽  
Power Efficient ◽  
Single Loop ◽  
Physiological Signal ◽  
Iot Applications

Purpose A third-order discrete time sigma delta modulator (SDM) is proposed with optimum performance by addressing instability and power dissipations issues, and a novel SDM architecture is designed and verified in behavioural modelling in MATLAB/SIMULINK environment. Simulation results show that performance parameters of proposed modulator achieved SNR of 105.41 dB, SNDR of 101.96 dB and DR of 17 bits for the signal bandwidth of 20 kHz. Design/methodology/approach This paper describes single-loop SDM design with optimum selection of integrator weights for physiological signal processing in IoT applications. Findings The proposed discrete time modulator designed with 1-bit quantizer and optimum oversampling ratio proved as power efficient. Integrator scaling coefficients are generated in LabVIEW environment for pure third-order noise shaping. Originality/value This paper contains the novelty in the work, and it is suitable for cognitive Internet of Things applications.

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