With the growing trend towards reducing the size of electronic devices, reducing power consumption has become one of the major concerns of circuit designers, and designing reversible circuits is one of the approaches proposed for reducing power consumption. Although several studies have been done in the field of synthesizing combinational reversible circuits, little work has been done for designing reversible sequential circuits. Furthermore, many researches in this context use traditional designs which replace latches, flip-flops and associated combinational gates with their reversible counterparts. This traditional technique is not very promising, because it leads to high quantum cost (QC) and garbage outputs. Recently, researchers have proposed direct design of reversible sequential circuits using Reed Muller expressions to obtain next state output. Since most sequential circuits have multiple outputs, using common product terms between multiple outputs might decrease QC significantly. In this paper, a modular and low QC design for a synchronous reversible [Formula: see text]-bit up/down counter with parallel load capability is presented. In this design, the common terms among multiple outputs are used efficiently, which leads to a low QC for the counter. A general formula to evaluate the QC of our proposed reversible counter is presented. This result shows that in our proposed design by increasing the number of bits of counter ([Formula: see text], the QC increases linearly, while in previous works by increasing the number of bits of counter, the QC increases exponentially.
Fault Tolerance in Reversible Logic Circuits and Quantum Cost Optimization