Quantum Cost Optimization of Reversible Adder/Subtractor Using a Novel Reversible Gate

2017 ◽  
pp. 111-118 ◽  
Author(s):  
B. P. Bhuvana ◽  
V. S. Kanchana Bhaaskaran
Keyword(s):  
Cost Optimization ◽  
Quantum Cost ◽  
Reversible Gate

scholarly journals Fault Tolerance in Reversible Logic Circuits and Quantum Cost Optimization

2020 ◽  
Vol 39 (5) ◽  
pp. 1099-1116
Author(s):  
Kamaraj Arunachalam ◽  
Marichamy Perumalsamy ◽  
Kaviyashri K. Ponnusamy
Keyword(s):  
Fault Tolerance ◽  
Cost Optimization ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost

Efficient designs of reversible BCD to EX-3 Converter with low quantum cost in nanoscale

2020 ◽  
Vol 18 (05) ◽  
pp. 2050020 ◽  
Author(s):  
Mojtaba Noorallahzadeh ◽  
Mohammad Mosleh
Keyword(s):  
Quantum Computing ◽  
Optical Computing ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Computing Systems ◽  
Gate Count ◽  
Reversible Gate ◽  
Significant Research ◽  
Research Domain ◽  
Better Than

As an interesting and significant research domain, reversible logic is massively utilized in technologies, including optical computing, cryptography, quantum computing, nanotechnology, and so on. The realization of quantum computing is not possible without the implementation of reversible logic, and reversible designs are presented mainly to minimize the thermal loss because of the data input bits lost in the irreversible circuit. Digital converters, as the most important logic circuits, are used to connect computing systems with different binary codes. This paper first proposes a new reversible gate called Reversible Noorallahzadeh[Formula: see text]Mosleh Gate (RNMG). Then, using the proposed RNMG gate as well as existing NMG1, NMG6, and PG gates, three different designs of reversible Binary-Coded Decimal (BCD) to EX-3 code converter are proposed. Our results indicate that the proposed BCD to EX-3 code converters are superior to previous designs in terms of quantum cost. Moreover, the proposed converters are comparable or better than previous designs in terms of gate count, constant inputs, and garbage outputs.

scholarly journals Designing and Implementation of Efficient (2i x j) Reversible RAM-Array Module

2018 ◽  
Vol 7 (3.12) ◽  
pp. 808
Author(s):  
Srija Alla ◽  
Bharathi S H
Keyword(s):  
Power Dissipation ◽  
Vlsi Design ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Worst Case ◽  
Nano Technology ◽  
Flip Flop ◽  
Digital World ◽  
Reversible Gate ◽  
Cost Efficient

In the modern digital-world, power dissipation in microprocessors is becoming a significant challenge for the researchers to design an efficient reversible logic circuit. Thus, study on reversible logic design has been rapidly increased in present days for its application in Nano technology as well as in low energized VLSI design etc. In this current study, have realized a QC (i.e. quantum-cost) efficient (2i x j) reversible RAM array module with (3 x 3) New Modified Fredkin (NMF) reversible gate. Additionally, have introduced a Reversible D-Flip-Flop (RDFF) with less QC, and Reversible (i x 2i) decoder which produces the effective results in terms of QC and garbage-outputs. Finally, the study analyzed the designed architecture in terms of worst case delay.  

scholarly journals Efficient Designs of Quantum Adder/Subtractor Using Universal Reversible Gate on IBM Q

Symmetry ◽  
2021 ◽  
Vol 13 (10) ◽  
pp. 1842
Author(s):  
Mohamed Osman ◽  
Khaled El-Wazan
Keyword(s):  
Quantum Computing ◽  
Symmetric Group ◽  
Success Probability ◽  
Quantum Cost ◽  
Logical Operations ◽  
Gate Count ◽  
Reversible Gate ◽  
Addition And Subtraction ◽  
Logic Unit ◽  
Ibm Quantum Experience

Reversible arithmetic and logic unit (ALU) is a necessary part of quantum computing. In this work, we present improved designs of reversible half and full addition and subtraction circuits. The proposed designs are based on a universal one type gate (G gate library). The G gate library can generate all possible permutations of the symmetric group. The presented designs are multi-function circuits that are capable of performing additional logical operations. We achieve a reduction in the quantum cost, gate count, number of constant inputs, and delay with zero garbage, compared to relevant results obtained by others. The experimental results using IBM Quantum Experience (IBM Q) illustrate the success probability of the proposed designs.

The Quantum Cost Optimized Design of 2:4 Decoder Using the New Reversible Logic Block

2020 ◽  
Vol 12 (3) ◽  
pp. 146-148
Author(s):  
Heranmoy Maity ◽  
Arindam Biswas ◽  
Arup K. Bhattacharjee ◽  
Anita Pal
Keyword(s):  
Logic Gate ◽  
Quantum Circuit ◽  
Reversible Logic ◽  
Optimized Design ◽  
Quantum Cost ◽  
Constant Input ◽  
Logic Block ◽  
Reversible Gate ◽  
Garbage Output

Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block. Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block. Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.

Testable Novel Parity-Preserving Reversible Gate and Low-Cost Quantum Decoder Design in 1D Molecular-QCA

2017 ◽  
Vol 26 (09) ◽  
pp. 1750145 ◽  
Author(s):  
Neeraj Kumar Misra ◽  
Bibhash Sen ◽  
Subodh Wairya ◽  
Bandan Bhoi
Keyword(s):  
Circuit Design ◽  
Low Cost ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Quantum Cost ◽  
Gate Count ◽  
Reversible Gate ◽  
Majority Voter ◽  
Decoder Design ◽  
Decoder Circuit

In this era of emerging technology, reversible logic is applied for circuit design. Due to the deep submicron and scaling, a number of pitfalls are faced by the CMOS technology. So a lot of constraints related to CMOS are stated with the QCA technology. The aim of this paper is the efficient conservative reversible decoder circuit design with optimal reversible metrics. It aims at furnishing a proposed DC gate (DC stands for decoder comparator) to help the construction of these mentioned circuits. Finally, the DC is employed to construct the [Formula: see text]-bit reversible decoder. Moreover, a new concept of the quantum equivalent of combined reversible gates is presented by the algorithm. By the comparative outcomes, it is found that the proposed decoder had achieved 25% quantum cost, 66% gate count, and 50% garbage outputs as compared to the counterpart. Further, stuck-at-fault for the single- and multiple-bit input and output is applied to the DC gate for testability. Moreover, the DC gate in the physical foreground on QCADesigner achieved 0.63 μm2 area, 15 majority voter gates, and 451 cell complexities. It is observed that nanoelectronics has also made an inevitable contribution in the area of QCA.

Design of BCD to Excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate

2018 ◽  
Vol 16 (07) ◽  
pp. 1850061 ◽  
Author(s):  
Heranmoy Maity ◽  
Arindam Biswas ◽  
Anita Pal ◽  
Anup Kumar Bhattacharjee
Keyword(s):  
Logic Gate ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Constant Input ◽  
Code Converter ◽  
Reversible Circuit ◽  
Reversible Gate ◽  
Garbage Output ◽  
Feynman Gate

In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible logic gate. BCD to Excess-3 code can be generated by adding “0011” to BCD number, but in the proposed work, addition is not required. The proposed reversible circuit can be designed using peres gate, Feynman gate and NOT gate optimized quantum cost, garbage output and constant input. The quantum cost (QC), garbage output and constant input of proposed reversible BCD to Excess-3 code converter are respectively 14, 1 and 1 which is better with respect to previously reported results. The improvement is, respectively 0–65%, 66.66–91.66% and 66.66–87.5%.

scholarly journals Synthesis Strategy of Reversible Circuits on DNA Computers

Symmetry ◽  
2021 ◽  
Vol 13 (7) ◽  
pp. 1242
Author(s):  
Mirna Rofail ◽  
Ahmed Younes
Keyword(s):  
Average Length ◽  
Logic Gates ◽  
Building Blocks ◽  
Quantum Cost ◽  
Reversible Circuits ◽  
Synthesis Strategy ◽  
Reversible Gate ◽  
Displacement Reactions ◽  
Reversible Logic Gates ◽  
Dna Computers

DNA computers and quantum computers are gaining attention as alternatives to classical digital computers. DNA is a biological material that can be reprogrammed to perform computing functions. Quantum computing performs reversible computations by nature based on the laws of quantum mechanics. In this paper, DNA computing and reversible computing are combined to propose novel theoretical methods to implement reversible gates and circuits in DNA computers based on strand displacement reactions, since the advantages of reversible logic gates can be exploited to improve the capabilities and functionalities of DNA computers. This paper also proposes a novel universal reversible gate library (URGL) for synthesizing n-bit reversible circuits using DNA to reduce the average length and cost of the constructed circuits when compared with previous methods. Each n-bit URGL contains building blocks to generate all possible permutations of a symmetric group of degree n. Our proposed group (URGL) in the paper is a permutation group. The proposed implementation methods will improve the efficiency of DNA computer computations as the results of DNA implementations are better in terms of quantum cost, DNA cost, and circuit length.

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