A low power variable sized CSLA implementation using GDI logic in 45nm SOI technology

2015 ◽  
Author(s):  
Jubal Saji ◽  
Shoaib Kamal
Keyword(s):  
Low Power ◽  
Soi Technology

scholarly journals Linearization Technique of Low Power Opamps in CMOS FD-SOI Technologies

2021 ◽  
Author(s):  
Wieslaw Kuzmicz
Keyword(s):  
Low Power ◽  
Negative Feedback ◽  
Operational Amplifiers ◽  
Back Gate ◽  
Linearization Technique ◽  
Mos Devices ◽  
Soi Technology

Negative feedback to the back gate of MOS devices available in FD-SOI technologies can be used to improve linearity of operational amplifiers. Two operational amplifiers designed and fabricated in a 22nm FD-SOI technology illustrate this technique, its advantages and limitations.

Planar fully depleted SOI technology: The convergence of high performance and low power towards multimedia mobile applications

2012 ◽  
Author(s):  
Bertrand Pelloux-Prayer ◽  
Milovan Blagojevic ◽  
Olivier Thomas ◽  
Amara Amara ◽  
Andrei Vladimirescu ◽  
...  
Keyword(s):  
Low Power ◽  
Mobile Applications ◽  
High Performance ◽  
Fully Depleted ◽  
Soi Technology
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