A 3.5GHz High Power GaN Hybrid Doherty Power Amplifier with Dynamic Input Power Splitting for Enhanced Power Added Efficiency at Backoff

Author(s):  
J. Romero Lopera ◽  
J. Mayock ◽  
Q. Sun ◽  
M. Gadringer ◽  
W. Bosch ◽  
...  
Author(s):  
Seyedehmarzieh Rouhani ◽  
Kasra Rouhi ◽  
Adib Abrishamifar ◽  
Majid Tayarani

This paper presents an approach to power added efficiency (PAE) increase for Quasi-Doherty power amplifier (Q-DPA) design. For this aim, active feedback is utilized instead of a passive quarter wavelength transmission line (TL) usage, which is conventionally used in the DPA schematic. PAE increase can be done by applying an accurate load modulation to the main amplifier (PAmain), especially for technologies in which output impedance of the main power amplifier (Zout,main) considerably varies in both low and high power regions. Because such precise modulation is still based on a modified TL, this approach suffers from the inherent narrowband behavior of that TL. As a consequence, expecting a wideband DPA may not be satisfied in all cases. To deal with this issue, active feedback is used to play a role in reaching PAmain, which is not saturated before, to its maximum efficiency at the highest level of received input power (Pin) in the high power region. Following Zout,main trajectories in power and frequency sweeps simultaneously just by a passive TL are not needed anymore. Still, for the sake of preventing total PAE degradation due to the consummated power by the feedback path’s power amplifier (PAfeedback) should be limited, analytical confinement is provided in this work. A comparison is made between GaAs pHEMT 0.25um MMIC technology-based conventional DPA and the proposed revised approach based-DPA to verify the mentioned approach. The proposed PA shows maximum output power of 33.4 dBm, maximum PAE of 41.6, fractional bandwidth of 11%. The Q-DPA works with a maximum power gain of 24.16.


2021 ◽  
Author(s):  
Pouya Jahanian ◽  
Azadeh Norouzi Kangarshahi

Abstract In this paper, an attempt has been made to design a Doherty power amplifier (DPA) with high-gain and wide-band. For this purpose, two peak amplifiers are used to improve the performance of the main amplifier. Main and auxiliary amplifiers with the same structure to the class-AB type and by using micro-strip lines in place of input/output and load matching networks, transmission lines and inductors of drain and gate, that minimize the losses in the DPA. The current DPA is implemented with GaN_HEMT_CLF1G0530_100v transistor and Rogers4003 substrate, which for 1GHz frequency in 0.5-1.5GHz bandwidth will be able to be at P-1dB point (this point, input power as 30dBm and output power as 47.98dBm) increase Drain efficiency and Power added efficiency (PAE) to 81.95% and 80.73%, respectively. The DPA helps to expand the back-off region and extend the linearity region, so the Peak to average power ratio (PAPR) will be 5.21dB and the Adjacent channel power ratio (ACPR) as 58.7dBc. A gain of 17.06-17.92dB was also obtained, which is significant compared to the results of similar samples.


Author(s):  
Seyedehmarzieh Rouhani ◽  
Kasra Rouhi ◽  
Adib Abrishamifar ◽  
Majid Tayarani

In this work, a premise is applied to the conventional load modulation equation of Doherty power amplifier (DPA) in 0.25 m GaAs pHEMT technology to compensate output impedance of main amplifier ( Z out,main ) variation, even in low power region. Using this modified modulation leads to the DPAs power added efficiency (PAE) increase in comparison by the case in which the load modulation revision is ignored, which is also designed in this paper. Second harmonic rejection networks are also added to both designs to play their roles as to efficiency increase. By doing so, the revised load modulation based DPA has the maximum PAE of 39.6%, maximum output power ( P out ) of 31.61dBm, at 8 GHz. Simulation results of this DPA in higher harmonics indicate the designed DPA has the minimum second and third harmonics power of -51.7 dBm and -80 dBm, respectively. For the sake of linearity evaluation, it is depicted that 1dB-power gain compression has not occurred in the input power (P in ) range in which the proposed DPA works.


Frequenz ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Shiwei Zhao ◽  
Jun Guan ◽  
Xiaoqi Zhou ◽  
Yuehang Xu

Abstract In this paper, a new reconfigurable power divider (PD) is proposed to improve the efficiency of the three-way Doherty power amplifier (DPA). The conventional λ/4 transmission line is replaced by the proposed reconfigurable PD in the input of peaking amplifier, where the 90° phase shift and impedance matching can be achieved. Furthermore, the output power distribution ratio (PDR) can be continuously adjusted in a large range by adjusting the reverse voltage of the varactor diodes. Therefore, the reconfigurable PD with the best PDR can assign input power to the peaking amplifier. Experiment results show that the maximum measured power added efficiency (PAE) of the proposed three-way DPA is 49%, which is improved by 5% compared with conventional three-way DPA.


Author(s):  
Edon Derguti ◽  
Erdin Ture ◽  
Sebastian Krause ◽  
Dirk Schwantuschke ◽  
Rudiger Quay ◽  
...  

Author(s):  
Edon Derguti ◽  
Erdin Ture ◽  
Sebastian Krause ◽  
Dirk Schwantuschke ◽  
Rudiger Quay ◽  
...  

2021 ◽  
Vol 11 (19) ◽  
pp. 9017
Author(s):  
Jinho Jeong ◽  
Yeongmin Jang ◽  
Jongyoun Kim ◽  
Sosu Kim ◽  
Wansik Kim

In this paper, a high-power amplifier integrated circuit (IC) in gallium-nitride (GaN) on silicon (Si) technology is presented at a W-band (75–110 GHz). In order to mitigate the losses caused by relatively high loss tangent of Si substrate compared to silicon carbide (SiC), low-impedance microstrip lines (20–30 Ω) are adopted in the impedance matching networks. They allow for the impedance transformation between 50 Ω and very low impedances of the wide-gate transistors used for high power generation. Each stage is matched to produce enough power to drive the next stage. A Lange coupler is employed to combine two three-stage common source amplifiers, providing high output power and good input/output return loss. The designed power amplifier IC was fabricated in the commercially available 60 nm GaN-on-Si high electron mobility transistor (HEMT) foundry. From on-wafer probe measurements, it exhibits the output power higher than 26.5 dBm and power added efficiency (PAE) higher than 8.5% from 88 to 93 GHz with a large-signal gain > 10.5 dB. Peak output power is measured to be 28.9 dBm with a PAE of 13.3% and a gain of 9.9 dB at 90 GHz, which corresponds to the power density of 1.94 W/mm. To the best of the authors’ knowledge, this result belongs to the highest output power and power density among the reported power amplifier ICs in GaN-on-Si HEMT technologies operating at the W-band.


Circuit World ◽  
2019 ◽  
Vol 46 (1) ◽  
pp. 1-5
Author(s):  
Yanfeng Fang ◽  
Yijiang Zhang

Purpose This paper aims to implement a new high output power fully integrated 23.1 to 27.2 GHz gallium arsenide heterojunction bipolar transistor power amplifier (PA) to meet the stringent linearity requirements of LTE systems. Design/methodology/approach The direct input power dividing technique is used on the chip. Broadband input and output matching techniques are used for broadband Doherty operation. Findings The PA achieves a small-signal gain of 22.8 dB at 25.1 GHz and a saturated output power of 24.3 dBm at 25.1 GHz with a maximum power added efficiency of 31.7%. The PA occupies 1.56 mm2 (including pads) and consumes a maximum current of 79.91 mA from a 9 V supply. Originality/value In this paper, the author proposed a novel direct input dividing technique with broadband matching circuits using a low Q output matching technique, and demonstrated a fully-integrated Doherty PA across frequencies of 23.1∼27.2 GHz for long term evolution-license auxiliary access (LTE-LAA) handset applications.


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