scholarly journals Extended Bandwidth and Increased Efficiency Quasi-Doherty Power Amplifier Design With A Revised Approach For Load Modulation

2021 ◽  
Author(s):  
Seyedehmarzieh Rouhani ◽  
Kasra Rouhi ◽  
Adib Abrishamifar ◽  
Majid Tayarani
Keyword(s):  
Power Amplifier ◽  
High Power ◽  
Maximum Output Power ◽  
Input Power ◽  
Maximum Efficiency ◽  
Maximum Output ◽  
Power Added Efficiency ◽  
Active Feedback ◽  
Doherty Power Amplifier ◽  
Load Modulation

This paper presents an approach to power added efficiency (PAE) increase for Quasi-Doherty power amplifier (Q-DPA) design. For this aim, active feedback is utilized instead of a passive quarter wavelength transmission line (TL) usage, which is conventionally used in the DPA schematic. PAE increase can be done by applying an accurate load modulation to the main amplifier (PAmain), especially for technologies in which output impedance of the main power amplifier (Zout,main) considerably varies in both low and high power regions. Because such precise modulation is still based on a modified TL, this approach suffers from the inherent narrowband behavior of that TL. As a consequence, expecting a wideband DPA may not be satisfied in all cases. To deal with this issue, active feedback is used to play a role in reaching PAmain, which is not saturated before, to its maximum efficiency at the highest level of received input power (Pin) in the high power region. Following Zout,main trajectories in power and frequency sweeps simultaneously just by a passive TL are not needed anymore. Still, for the sake of preventing total PAE degradation due to the consummated power by the feedback path’s power amplifier (PAfeedback) should be limited, analytical confinement is provided in this work. A comparison is made between GaAs pHEMT 0.25um MMIC technology-based conventional DPA and the proposed revised approach based-DPA to verify the mentioned approach. The proposed PA shows maximum output power of 33.4 dBm, maximum PAE of 41.6, fractional bandwidth of 11%. The Q-DPA works with a maximum power gain of 24.16.

scholarly journals Increased Efficiency of a Current Compensating Load Modulation Based MMIC Doherty Power Amplifier Design In 0.25m GaAs pHEMT Technology

2020 ◽  
Author(s):  
Seyedehmarzieh Rouhani ◽  
Kasra Rouhi ◽  
Adib Abrishamifar ◽  
Majid Tayarani
Keyword(s):  
Power Amplifier ◽  
Second Harmonic ◽  
Maximum Output Power ◽  
Input Power ◽  
Maximum Output ◽  
Modulation Equation ◽  
Gain Compression ◽  
Power Added Efficiency ◽  
Doherty Power Amplifier ◽  
Load Modulation

In this work, a premise is applied to the conventional load modulation equation of Doherty power amplifier (DPA) in 0.25 m GaAs pHEMT technology to compensate output impedance of main amplifier ( Z out,main ) variation, even in low power region. Using this modified modulation leads to the DPAs power added efficiency (PAE) increase in comparison by the case in which the load modulation revision is ignored, which is also designed in this paper. Second harmonic rejection networks are also added to both designs to play their roles as to efficiency increase. By doing so, the revised load modulation based DPA has the maximum PAE of 39.6%, maximum output power ( P out ) of 31.61dBm, at 8 GHz. Simulation results of this DPA in higher harmonics indicate the designed DPA has the minimum second and third harmonics power of -51.7 dBm and -80 dBm, respectively. For the sake of linearity evaluation, it is depicted that 1dB-power gain compression has not occurred in the input power (P in ) range in which the proposed DPA works.

scholarly journals Design and simulate a doherty power amplifier using GaAs technology for telecommunication applications

2019 ◽  
Vol 15 (2) ◽  
pp. 845
Author(s):  
Ehsan Barmala
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Power Amplifiers ◽  
High Efficiency ◽  
Maximum Output Power ◽  
Input Power ◽  
Power Divider ◽  
Maximum Efficiency ◽  
Maximum Output ◽  
Doherty Power Amplifier

<span>In this paper, a Doherty power amplifier was designed and simulated at 2.4 GHz central frequency which has high efficiency. A Doherty power amplifier is a way to increase the efficiency in the power amplifiers. OMMIC ED02AH technology and PHEMT transistors, which is made of gallium arsenide, have been used in this simulation. The Doherty power amplifier unique feature is its simple structure which is consisting of two parallel power amplifiers and transmission lines. In order to integrate the circuit, the Doherty power transmission amplifier lines were implemented using an inductor and capacitive components. Also, the Wilkinson power divider is used on the chip input. To improve the efficiency, the auxiliary amplifier dimensions is selected enlarge and the further input power is allocated it by the power divider. A parallel R-C circuit has been used at the input of transistors to improve their stability. Simulation results show that the Doherty power amplifier has 17.2 dB output power gain, 23 dBm maximum output power, and its output power P<sub>1dB</sub> =22.6dBm at compression point -1 dB, also, its maximum efficiency is 55.5%.</span>

scholarly journals Ultra-Compact mm-Wave Monolithic IC Doherty Power Amplifier for Mobile Handsets

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2131
Author(s):  
Maryam Sajedin ◽  
Issa Elfergani ◽  
Jonathan Rodriguez ◽  
Raed Abd-Alhameed ◽  
Monica Fernandez-Barciela ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Power Amplifier ◽  
Second Harmonic ◽  
Maximum Output Power ◽  
Maximum Output ◽  
Fully Integrated ◽  
Monolithic Microwave Integrated Circuits ◽  
Power Added Efficiency ◽  
Load Modulation ◽  
Mobile Handset

This work develops a novel dynamic load modulation Power Amplifier (PA) circuity that can provide an optimum compromise between linearity and efficiency while covering multiple cellular frequency bands. Exploiting monolithic microwave integrated circuits (MMIC) technology, a fully integrated 1W Doherty PA architecture is proposed based on 0.1 μm AlGaAs/InGaAs Depletion-Mode (D-Mode) technology provided by the WIN Semiconductors foundry. The proposed wideband DPA incorporates the harmonic tuning Class-J mode of operation, which aims to engineer the voltage waveform via second harmonic capacitive load termination. Moreover, the applied post-matching technique not only reduces the impedance transformation ratio of the conventional DPA, but also restores its proper load modulation. The simulation results indicate that the monolithic drive load modulation PA at 4 V operation voltage delivers 44% PAE at the maximum output power of 30 dBm at the 1 dB compression point, and 34% power-added efficiency (PAE) at 6 dB power back-off (PBO). A power gain flatness of around 14 ± 0.5 dB was achieved over the frequency band of 23 GHz to 27 GHz. The compact MMIC load modulation technique developed for the 5G mobile handset occupies the die area of 3.2 mm2.

A fully matched dual stage CMOS power amplifier with integrated passive linearizer attaining 23 db gain, 40% PAE and 28 DBM OIP3

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Premmilaah Gunasegaran ◽  
Jagadheswaran Rajendran ◽  
Selvakumar Mariappan ◽  
Yusman Mohd Yusof ◽  
Zulfiqar Ali Abdul Aziz ◽  
...  
Keyword(s):  
Power Consumption ◽  
Output Power ◽  
Power Amplifier ◽  
Maximum Output Power ◽  
Maximum Output ◽  
Power Gain ◽  
Matching Network ◽  
Content Type ◽  
Power Added Efficiency ◽  
Main Amplifier

Purpose The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA). Design/methodology/approach The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability. Findings With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation. Practical implications The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design. Originality/value The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

Concurrent dual-band SiGe HBT power amplifier for Wireless applications

2009 ◽  
Vol 1 (2) ◽  
pp. 117-126 ◽  
Author(s):  
Vittorio Camarchia ◽  
Rocco Giofrè ◽  
Iacopo Magrini ◽  
Luca Piazzon ◽  
Alessandro Cidronali ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Orthogonal Frequency Division Multiplexing ◽  
Maximum Output Power ◽  
System Level ◽  
Dual Band ◽  
Maximum Output ◽  
System Architectures ◽  
Power Added Efficiency ◽  
Mode Operation

This paper presents an investigation of a concurrent low-cost dual-band power amplifier (PA) fabricated in SiGe technology, able to simultaneously operate at two frequencies of 2.45 and 3.5-GHz, including an evaluation of its system level performance potentiality. Taking into account the technology novelty and the lack of device characterization and modeling, a hybrid (MIC) approach has been adopted both for a fast prototyping of the PA and for the evaluation of the device potentiality based on an extensive linear and nonlinear characterization. The comparison of PA performance in single-band or concurrent mode operation will be presented. In particular, the measured PA prototype shows an output power of 17.2 and 17-dBm at a 1-dB compression point, at 2.45 and 3.5-GHz, respectively, for CW single-mode operation, with a power added efficiency around 20%. System-level analysis predicts that, when the PA is operated under the 20-MHz Orthogonal Frequency-Division Multiplexing (OFDM) concurrent signals, the maximum output power levels to maintain the Error Vector Magnitude (EVM) within 5% are 11 and 3.5-dBm at 2.45 and 3.5-GHz, respectively. Moreover, new concepts and possible new system architectures for the development of the next generation of the multi-band transceiver front-end will be provided with an extensive system-level evaluation of the amplifier.

scholarly journals A Wide-Band High-Gain Doherty Power Amplifier With Class-AB HEMT Amplifiers

2021 ◽  
Author(s):  
Pouya Jahanian ◽  
Azadeh Norouzi Kangarshahi
Keyword(s):  
Power Amplifier ◽  
Transmission Lines ◽  
Average Power ◽  
Wide Band ◽  
High Gain ◽  
Input Power ◽  
Power Ratio ◽  
Class Ab ◽  
Power Added Efficiency ◽  
Doherty Power Amplifier

Abstract In this paper, an attempt has been made to design a Doherty power amplifier (DPA) with high-gain and wide-band. For this purpose, two peak amplifiers are used to improve the performance of the main amplifier. Main and auxiliary amplifiers with the same structure to the class-AB type and by using micro-strip lines in place of input/output and load matching networks, transmission lines and inductors of drain and gate, that minimize the losses in the DPA. The current DPA is implemented with GaN_HEMT_CLF1G0530_100v transistor and Rogers4003 substrate, which for 1GHz frequency in 0.5-1.5GHz bandwidth will be able to be at P-1dB point (this point, input power as 30dBm and output power as 47.98dBm) increase Drain efficiency and Power added efficiency (PAE) to 81.95% and 80.73%, respectively. The DPA helps to expand the back-off region and extend the linearity region, so the Peak to average power ratio (PAPR) will be 5.21dB and the Adjacent channel power ratio (ACPR) as 58.7dBc. A gain of 17.06-17.92dB was also obtained, which is significant compared to the results of similar samples.

A 5.2/5.8 GHz Dual Band On-Off Keying Transmitter Design for Bio-Signal Transmission

2018 ◽  
Vol 3 (2) ◽  
Author(s):  
Chang-Hsi Wu ◽  
Hong-Cheng You ◽  
Shun-Zhao Huang
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Power Efficiency ◽  
Supply Voltage ◽  
Maximum Output Power ◽  
Dual Band ◽  
Maximum Output ◽  
Power Combiner ◽  
Power Added Efficiency ◽  
Chip Size

Abstract An architecture of 5.2/5.8-GHz dual-band on-off keying (DBOOK) modulated transmitter is designed in a 0.18-μm CMOS technology. The proposed DBOOK transmitter is used in the biosignal transmission system with high power efficiency and small area. To reduce power consumption and enhance output swing, two pairs of center-tapped transformers are used as both LC tank and source grounding choke for the designed voltage controlled oscillator (VCO). Switching capacitances are used to achieve dual band operations, and a complemented power combiner is used to merge the differential output power of VCO to a single-ended output. Besides, the linearizer circuits are used in the proposed power amplifier with wideband output matching to improve the linearity both at 5.2/5.8-GHz bands. The designed DBOOK transmitter is implemented by dividing it into two chips. One chip implements the dual-band switching VCO and power combiner, and the other chip implements a linear power amplifier including dual-band operation. The first chip drives an output power of 2.2mW with consuming power of 5.13 mW from 1.1 V supply voltage. With the chip size including pad of 0.61 × 0.91 m2, the measured data rate and transmission efficiency attained are 100 Mb/s and 51 pJ/bit, respectively. The second chip, for power enhanced mode, exhibits P1 dB of −9 dBm, IIP3 of 1 dBm, the output power 1 dB compression point of 12.42 dBm, OIP3 of about 21 dBm, maximum output power of 17.02/16.18 dBm, and power added efficiency of 17.13/16.95% for 5.2/ 5.8 GHz. The chip size including pads is 0:693 × 1:084mm2.

A High Temperature Linear Wideband Power Amplifier for a Downhole Communication System

2017 ◽  
Vol 2017 (HiTEN) ◽  
pp. 000114-000117
Author(s):  
S. Reza Hiemstra ◽  
Brannon M. Kerrigan ◽  
Dong S. Ha
Keyword(s):  
Ambient Temperature ◽  
Power Amplifier ◽  
Communication System ◽  
Oil And Gas ◽  
Maximum Output Power ◽  
Oil And Gas Industry ◽  
Junction Temperature ◽  
Maximum Output ◽  
Gas Industry ◽  
Power Added Efficiency

Abstract In order to reach previously untapped wells, the oil and gas industry continues to drill deeper, resulting in extreme operating temperatures for electronic systems. It is essential for electronic circuits and systems to be able to withstand extreme temperatures. The proposed power amplifier (PA) intends for a downhole communication system operating at an ambient temperature of 230 °C. The proposed PA is designed with Qorvo T2G6003028-FL GaN on SiC HEMT, which offers a high junction temperature. The proposed PA can operate reliably up to an ambient temperature of 230 °C with the operation frequency from 228 MHz to 263 MHz. At 230 °C, it achieves maximum output power of 1.66 W, the peak gain of 24 dB, peak PAE (power added efficiency) of 25%, OP1dB (output 1-db compression point) of 32 dBm, and OIP3 (output third intercept point) of 37.9 dBm..

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