Design of a radiation tolerant library on micronic CMOS technology

This article presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 15.6 ps, fabricated in a 65 nm complementary metal oxide semiconductor (CMOS) technology. The TDC is based on a multipath pseudo differential ring oscillator with reduced phase delay, without the need for calibration or interpolation. The ring oscillator is placed inside a Phase Locked Loop (PLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation. Measurements to evaluate the performance of the TDC in terms of the total ionizing dose (TID) were done. Two different samples were irradiated up to a dose of 2.2 MGy SiO 2 while still maintaining a resolution of 15.6 ps. The TDC has a differential non-linearity (DNL) and integral non-linearity (INL) of 0.22 LSB rms and 0.34 LSB rms respectively.

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A Radiation-Tolerant, high performance SPAD for SiPMs implemented in CMOS technology

2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD) ◽

10.1109/nssmic.2016.8069762 ◽

2016 ◽

Cited By ~ 2

Author(s):

Yudong Li ◽

Chockalingam Veerappan ◽

Myung-Jae Lee ◽

Lin Wen ◽

Qi Guo ◽

...

Keyword(s):

High Performance ◽

Cmos Technology ◽

Radiation Tolerant

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A large dynamic range radiation-tolerant analog memory in a quarter-micron CMOS technology

IEEE Transactions on Nuclear Science ◽

10.1109/23.940095 ◽

2001 ◽

Vol 48 (3) ◽

pp. 435-439 ◽

Cited By ~ 9

Author(s):

G. Anelli ◽

F. Anghinolfi ◽

A. Rivetti

Keyword(s):

Dynamic Range ◽

Cmos Technology ◽

Large Dynamic Range ◽

Analog Memory ◽

Radiation Tolerant

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0.6 μm CMOS technology with radiation tolerant features application to 8 K×16 dual port RAM and sea of gates

Proceedings of the Third European Conference on Radiation and its Effects on Components and Systems ◽

10.1109/radecs.1995.509770 ◽

2002 ◽

Author(s):

T. Corbiere ◽

V. Lassere ◽

B. Thomas ◽

S. Hachad ◽

R. Ecoffet ◽

...

Keyword(s):

Cmos Technology ◽

Radiation Tolerant

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High-Speed, Radiation-Tolerant Laser Drivers in 0.13 $\mu$m CMOS Technology for HEP Applications

IEEE Transactions on Nuclear Science ◽

10.1109/tns.2014.2361679 ◽

2014 ◽

Vol 61 (6) ◽

pp. 3653-3659 ◽

Cited By ~ 6

Author(s):

Giovanni Mazza ◽

Filip Tavernier ◽

Paulo Moreira ◽

Daniela Calvo ◽

Paolo De Remigis ◽

...

Keyword(s):

High Speed ◽

Cmos Technology ◽

Laser Drivers ◽

Radiation Tolerant

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Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies

Electronics ◽

10.3390/electronics8040432 ◽

2019 ◽

Vol 8 (4) ◽

pp. 432 ◽

Cited By ~ 3

Author(s):

Jeffrey Prinzie ◽

Karel Appels ◽

Szymon Kulis

Keyword(s):

Integrated Circuits ◽

High Speed ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Deep Submicron ◽

Oxide Semiconductor ◽

Digital Integrated Circuits ◽

Physical Implementation ◽

Radiation Hard ◽

Radiation Tolerant

This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

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Novel Full TMR Placement Techniques for High-Speed Radiation Tolerant Digital Integrated Circuits

Electronics ◽

10.3390/electronics9111936 ◽

2020 ◽

Vol 9 (11) ◽

pp. 1936

Author(s):

Karel Appels ◽

Jeffrey Prinzie

Keyword(s):

Integrated Circuits ◽

High Speed ◽

Cmos Technology ◽

Digital Logic ◽

Radiation Environment ◽

Digital Integrated Circuits ◽

Distributed Approach ◽

Implementation Methodology ◽

Logic Cells ◽

Radiation Tolerant

This paper presents a novel physical implementation methodology for high-speed Triple Modular Redundant (TMR) digital integrated circuits for harsh radiation environment applications. An improved distributed approach is presented to constrain redundant branches of Triple Modular Redundant (TMR) digital logic cells using repetitive, interleaved micro-floorplans. To optimally constrain the placement of both sequential and combinational cells, the TMR netlist is used to segment the the logic into unrelated groups allowing sharing without compromising reliability. The technique was evaluated in a 65 nm bulk CMOS technology and a comparison is made to conventional methods.

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