scholarly journals Radiation Assessment of a 15.6ps Single-Shot Time-to-Digital Converter in Terms of TID

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 558 ◽  
Author(s):  
Bjorn Van Bockel ◽  
Jeffrey Prinzie ◽  
Paul Leroux
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Oxide Semiconductor ◽  
Single Shot ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Pvt Variations ◽  
Radiation Tolerant ◽  
Radiation Measurements

This article presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 15.6 ps, fabricated in a 65 nm complementary metal oxide semiconductor (CMOS) technology. The TDC is based on a multipath pseudo differential ring oscillator with reduced phase delay, without the need for calibration or interpolation. The ring oscillator is placed inside a Phase Locked Loop (PLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation. Measurements to evaluate the performance of the TDC in terms of the total ionizing dose (TID) were done. Two different samples were irradiated up to a dose of 2.2 MGy SiO 2 while still maintaining a resolution of 15.6 ps. The TDC has a differential non-linearity (DNL) and integral non-linearity (INL) of 0.22 LSB rms and 0.34 LSB rms respectively.

scholarly journals Current Measurement Transducer Based on Current-To-Voltage-To-Frequency Converting Ring Oscillator with Cascade Bias Circuit

Sensors ◽  
2020 ◽  
Vol 20 (2) ◽  
pp. 493
Author(s):  
Jongha Park ◽  
Jung-Hyun Park ◽  
Seong-Ook Jung
Keyword(s):  
Three Dimensional ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Measurement Range ◽  
Ring Oscillator ◽  
Oxide Semiconductor ◽  
Measurement Transducer ◽  
Current Output ◽  
Differential Nonlinearity ◽  
Rail To Rail

We propose a ring oscillator (RO) based current-to-voltage-to-frequency (I–V–F) converting current transducer with a cascade bias circuit. The I–V–F converting scheme guarantees highly stable biasing against RO, with a rail-to-rail output operation. This device was fabricated using National NanoFab Center (NNFC) 180 nm complementary metal-oxide-semiconductor (CMOS) technology, which achieves a current resolution of 1 nA in a measurement range up to 200 nA. A noise floor of 11.8 pA/√Hz, maximum differential nonlinearity (DNL) of 0.15 in 1 nA steps, and rail-to-rail output with a 1.8 V power supply is achieved. The proposed transducer can be effectively applied to bio-sensing devices requiring a compact area and low power consumption with a low current output. The fabricated structure can be applied to monolithic-three-dimensional integration with a bio-sensing device.

scholarly journals Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 432 ◽  
Author(s):  
Jeffrey Prinzie ◽  
Karel Appels ◽  
Szymon Kulis
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Oxide Semiconductor ◽  
Digital Integrated Circuits ◽  
Physical Implementation ◽  
Radiation Hard ◽  
Radiation Tolerant

This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

scholarly journals Performance Analysis of Ring Oscillators and Current-Starved VCO in 45-nm CMOS Technology

2022 ◽  
Vol 10 (1) ◽  
pp. 732-737
Author(s):  
Prakash Sharma
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Oxide Semiconductor ◽  
Center Frequency ◽  
Noise Power ◽  
Ring Oscillators ◽  
Voltage Controlled Oscillator

Abstract: This paper presents a relative study among two Ring oscillators architecture (CMOS, NMOS) and current-starved Voltage-controlled oscillator (CS-VCO) on the basis of different parameters like power dissipation ,phase noise etc. All the design has been done in 45- nm CMOS technology node and 2.3 GHz Centre frequency have been taken for the comparison because of their applications in AV Devices and Radio control. An inherent idea of the given performance parameters has been realize by thecomparative study. The comparative data shows that NMOS based Ring oscillator is good option in terms of the phase noise performance. In this study NMOS Ring Oscillator have attain a phase noise -97.94 dBc/Hz at 1 MHz offset frequency from 2.3 GHz center frequency. The related data also shows that CMOS Ring oscillator is the best option in terms of power consumption. In this work CMOS Ring oscillator evacuatea power of 1.73 mW which is quite low. Keywords: Voltage controlled oscillator (VCO), phase noise, power consumption, Complementary metal-oxide-semiconductor (CMOS), Current Starved Voltage-Controlled Oscillator (CS- VCO), Pull up network (PUN), Pull down network (PDN)

scholarly journals A massively scalable Time-to-Digital Converter with a PLL-free calibration system in a commercial 130 nm process

2021 ◽  
Vol 16 (11) ◽  
pp. P11023
Author(s):  
F. Martinelli ◽  
P. Valerio ◽  
R. Cardarelli ◽  
E. Charbon ◽  
G. Iacobucci ◽  
...  
Keyword(s):  
High Energy Physics ◽  
High Energy ◽  
Ring Oscillator ◽  
Single Shot ◽  
Digital Converter ◽  
Calibration System ◽  
Time To Digital Converter ◽  
Imaging Detector ◽  
Bicmos Technology ◽  
Massive Parallelization

Abstract A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. A novel version of this design is proposed, along with an analytical model of linearity. The model allowed us to understand the source of the performance superiority (in terms of linearity) of our design and to predict further improvements. The oscillator is integrated in a event-by-event self-calibration system that allows avoiding any PLL-based synchronization. For this reason and for the compactness and simplicity of the architecture, the proposed TDC is suitable for applications in which a large number of converters and a massive parallelization are required such as High-Energy Physics and medical imaging detector systems. A test chip for the TDC has been fabricated and tested. The TDC shows a DNL≤1.3 LSB, an INL≤2 LSB and a single-shot precision of 19.5 ps (0.58 LSB). The chip dissipates a power of 5.4 mW overall.

Computational study of the staircase molecular conductivity of polyoxovanadates adsorbed on Au(111)

2021 ◽  
Vol 50 (16) ◽  
pp. 5540-5551
Author(s):  
Almudena Notario-Estévez ◽  
Xavier López ◽  
Coen de Graaf
Keyword(s):  
Metal Oxide ◽  
Computational Study ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Molecular Conduction ◽  
Conduction Properties ◽  
Molecular Conductivity

This computational study presents the molecular conduction properties of polyoxovanadates V6O19 (Lindqvist-type) and V18O42, as possible successors of the materials currently in use in complementary metal–oxide semiconductor (CMOS) technology.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

Deep-Submicron Single-Gate Complementary Metal Oxide Semiconductor (CMOS) Technology Using Channel Preamorphization

1998 ◽  
Vol 37 (Part 1, No. 3B) ◽  
pp. 1050-1053 ◽  
Author(s):  
Masayasu Miyake ◽  
Toshio Kobayashi ◽  
Yutaka Sakakibara ◽  
Kimiyoshi Deguchi ◽  
Mitsutoshi Takahashi
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor

A 60 GHz reconfigurable active phase shifter based on a vector modulator in 65 nm CMOS technology

2016 ◽  
Vol 8 (3) ◽  
pp. 399-404 ◽  
Author(s):  
Boris Moret ◽  
Nathalie Deltimple ◽  
Eric Kerhervé ◽  
Baudouin Martineau ◽  
Didier Belot
Keyword(s):  
Phase Shift ◽  
Phase Shifter ◽  
Complementary Metal Oxide Semiconductor ◽  
Active Phase ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
60 Ghz ◽  
Semiconductor Technology ◽  
Vector Modulator ◽  
Active Phase Shifter

This paper presents a 60 GHz reconfigurable active phase shifter based on a vector modulator implemented in 65 nm complementary metal–oxide–semiconductor technology. This circuit is based on the recombination of two differential paths in quadrature. The proposed vector modulator allows us to generate a phase shift between 0° and 360°. The voltage gain varies between −13 and −9 dB in function of the phase shift generated with a static consumption between 26 and 63 mW depending on its configuration.

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