Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies

This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

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Novel Full TMR Placement Techniques for High-Speed Radiation Tolerant Digital Integrated Circuits

Electronics ◽

10.3390/electronics9111936 ◽

2020 ◽

Vol 9 (11) ◽

pp. 1936

Author(s):

Karel Appels ◽

Jeffrey Prinzie

Keyword(s):

Integrated Circuits ◽

High Speed ◽

Cmos Technology ◽

Digital Logic ◽

Radiation Environment ◽

Digital Integrated Circuits ◽

Distributed Approach ◽

Implementation Methodology ◽

Logic Cells ◽

Radiation Tolerant

This paper presents a novel physical implementation methodology for high-speed Triple Modular Redundant (TMR) digital integrated circuits for harsh radiation environment applications. An improved distributed approach is presented to constrain redundant branches of Triple Modular Redundant (TMR) digital logic cells using repetitive, interleaved micro-floorplans. To optimally constrain the placement of both sequential and combinational cells, the TMR netlist is used to segment the the logic into unrelated groups allowing sharing without compromising reliability. The technique was evaluated in a 65 nm bulk CMOS technology and a comparison is made to conventional methods.

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Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽

10.3390/mi12050551 ◽

2021 ◽

Vol 12 (5) ◽

pp. 551

Author(s):

Zhongjian Bian ◽

Xiaofeng Hong ◽

Yanan Guo ◽

Lirida Naviner ◽

Wei Ge ◽

...

Keyword(s):

Nonvolatile Memory ◽

High Speed ◽

Low Voltage ◽

Supply Voltage ◽

Random Access ◽

Magnetic Tunnel Junction ◽

Complementary Metal Oxide Semiconductor ◽

Current Mode ◽

Cmos Technology ◽

Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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Deep-Submicron Single-Gate Complementary Metal Oxide Semiconductor (CMOS) Technology Using Channel Preamorphization

Japanese Journal of Applied Physics ◽

10.1143/jjap.37.1050 ◽

1998 ◽

Vol 37 (Part 1, No. 3B) ◽

pp. 1050-1053 ◽

Cited By ~ 1

Author(s):

Masayasu Miyake ◽

Toshio Kobayashi ◽

Yutaka Sakakibara ◽

Kimiyoshi Deguchi ◽

Mitsutoshi Takahashi

Keyword(s):

Metal Oxide ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Deep Submicron ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor

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A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

Electronics ◽

10.3390/electronics8030305 ◽

2019 ◽

Vol 8 (3) ◽

pp. 305 ◽

Cited By ~ 1

Author(s):

Dong Wang ◽

Xiaoge Zhu ◽

Xuan Guo ◽

Jian Luan ◽

Lei Zhou ◽

...

Keyword(s):

High Speed ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Sar Adc ◽

Oxide Semiconductor ◽

Power Measurement ◽

Cmos Process ◽

Analog To Digital ◽

Full Speed ◽

Time Interleaved

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

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Radiation Assessment of a 15.6ps Single-Shot Time-to-Digital Converter in Terms of TID

Electronics ◽

10.3390/electronics8050558 ◽

2019 ◽

Vol 8 (5) ◽

pp. 558 ◽

Cited By ~ 3

Author(s):

Bjorn Van Bockel ◽

Jeffrey Prinzie ◽

Paul Leroux

Keyword(s):

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Ring Oscillator ◽

Oxide Semiconductor ◽

Single Shot ◽

Digital Converter ◽

Time To Digital Converter ◽

Pvt Variations ◽

Radiation Tolerant ◽

Radiation Measurements

This article presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 15.6 ps, fabricated in a 65 nm complementary metal oxide semiconductor (CMOS) technology. The TDC is based on a multipath pseudo differential ring oscillator with reduced phase delay, without the need for calibration or interpolation. The ring oscillator is placed inside a Phase Locked Loop (PLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation. Measurements to evaluate the performance of the TDC in terms of the total ionizing dose (TID) were done. Two different samples were irradiated up to a dose of 2.2 MGy SiO 2 while still maintaining a resolution of 15.6 ps. The TDC has a differential non-linearity (DNL) and integral non-linearity (INL) of 0.22 LSB rms and 0.34 LSB rms respectively.

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A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology

Journal of Circuits System and Computers ◽

10.1142/s0218126619501652 ◽

2019 ◽

Vol 28 (10) ◽

pp. 1950165 ◽

Cited By ~ 3

Author(s):

Sandeep Garg ◽

Tarun K. Gupta

Keyword(s):

Low Power ◽

High Speed ◽

Supply Voltage ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Power Reduction ◽

Maximum Power ◽

Oxide Semiconductor ◽

Domino Logic ◽

Maximum Delay

In this paper, a fin field-effect transistor (FinFET)-based domino technique dynamic node-driven feedback transistor domino logic (DNDFTDL) is designed for low-power, high-speed and improved noise performance. In the proposed domino technique, the concept of current division is explored below the evaluation network for enhancement of performance parameters. Simulations are carried out for 32-nm complementary metal–oxide–semiconductor (CMOS) and FinFET node using HSPICE for 2-, 4-, 8- and 16-input OR gates with a DC supply voltage of 0.9[Formula: see text]V. Proposed technique shows a maximum power reduction of 73.93% in FinFET short-gate (SG) mode as compared to conditional stacked keeper domino logic (CSKDL) technique and a maximum power reduction of 72.12% as compared to modified high-speed clocked delay domino logic (M-HSCD) technique in FinFET low-power (LP) mode. The proposed technique shows a maximum delay reduction of 35.52% as compared to voltage comparison domino (VCD) technique in SG mode and a reduction of 25.01% as compared to current mirror footed domino logic (CMFD) technique in LP mode. The unity noise gain (UNG) of the proposed circuit is 1.72–[Formula: see text] higher compared to different existing techniques in FinFET SG mode and is 1.42–[Formula: see text] higher in FinFET LP mode. The Figure of Merit (FOM) of the proposed circuit is up to [Formula: see text] higher as compared to existing domino logic techniques because of lower values of power, delay and area and higher values of UNG of the proposed circuit. In addition, the proposed technique shows a maximum power reduction of up to 68.64% in FinFET technology as compared to its counterpart in CMOS technology.

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High-speed programmable photonic circuits in a cryogenically compatible, visible–near-infrared 200 mm CMOS architecture

Nature Photonics ◽

10.1038/s41566-021-00903-x ◽

2021 ◽

Author(s):

Mark Dong ◽

Genevieve Clark ◽

Andrew J. Leenheer ◽

Matthew Zimmermann ◽

Daniel Dominguez ◽

...

Keyword(s):

Integrated Circuits ◽

Power Consumption ◽

High Speed ◽

Large Scale ◽

Near Infrared ◽

Response Times ◽

Photonic Integrated Circuits ◽

Complementary Metal Oxide Semiconductor ◽

Phase Shifters ◽

Oxide Semiconductor

AbstractRecent advances in photonic integrated circuits have enabled a new generation of programmable Mach–Zehnder meshes (MZMs) realized by using cascaded Mach–Zehnder interferometers capable of universal linear-optical transformations on N input/output optical modes. MZMs serve critical functions in photonic quantum information processing, quantum-enhanced sensor networks, machine learning and other applications. However, MZM implementations reported to date rely on thermo-optic phase shifters, which limit applications due to slow response times and high power consumption. Here we introduce a large-scale MZM platform made in a 200 mm complementary metal–oxide–semiconductor foundry, which uses aluminium nitride piezo-optomechanical actuators coupled to silicon nitride waveguides, enabling low-loss propagation with phase modulation at greater than 100 MHz in the visible–near-infrared wavelengths. Moreover, the vanishingly low hold-power consumption of the piezo-actuators enables these photonic integrated circuits to operate at cryogenic temperatures, paving the way for a fully integrated device architecture for a range of quantum applications.

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A novel design of nano router with high-speed crossbar scheduler for digital systems in QCA paradigm

Circuit World ◽

10.1108/cw-10-2020-0280 ◽

2021 ◽

Vol ahead-of-print (ahead-of-print) ◽

Author(s):

Kalpana Kasilingam ◽

Paulchamy Balaiah

Keyword(s):

High Speed ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Modern Technology ◽

Oxide Semiconductor ◽

Large Area ◽

Content Type ◽

Compact Size ◽

High Power Consumption ◽

High Speed Data

Purpose The nano-router would be a mastery device for providing high-speed data delivery. Here nano-router with a space-efficient crossbar scheduler is used for making absolutely less consumption in power. Design/methodology/approach In the emerging modern technology, every one of us is expecting a delivery of data at a high speed. To achieve high-speed delivery the authors are using the router. The router used here is at nanoscale reading which provides a compact size. Findings This can be implemented using the modern tools called Quantum-dot Cellular Automata (QCA) which is operated without the use of a transistor. As conventional complementary metal oxide semiconductor (CMOS) designs have some limitations such as low density, high power consumption and requirement of a large area. Research limitations/implications To overcome these limitations the QCA is used. It characterizes capability is used to substituting CMOS technology. The round-robin fashion is used in a high-speed space-efficient crossbar scheduler. Practical implications The simulation of the planned circuit with notional information established the practical identity of the scheme. Social implications The proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool. Originality/value The proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool. In this work, the performance of the router can be done in both the QCA environment and CMOS technology.

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A modified prefix operator well suited for area-efficient brick-based adder implementations

Advances in Radio Science ◽

10.5194/ars-9-289-2011 ◽

2011 ◽

Vol 9 ◽

pp. 289-295

Author(s):

I. Rust ◽

T. G. Noll

Keyword(s):

Integrated Circuits ◽

High Speed ◽

Short Circuit ◽

Cmos Technology ◽

Deep Submicron ◽

Classical Operator ◽

Signal Combination ◽

Short Circuit Currents ◽

Prefix Adders ◽

Sub Wavelength

Abstract. The implementation of integrated circuits becomes more and more difficult in the Ultra-Deep-Submicron regime due to sub-wavelength lithography issues. An approach called Brick-Based Design was recently proposed to eliminate the disadvantages of staying with the classical approach to layout design. Prefix adders are a core component in a wide variety of applications due to their high speed and regular topology. In this paper, a modified prefix operator for prefix adders is proposed which is well suited for brick-style layout implementation and, in addition, offers an increase in efficiency. The proposed operator makes it possible to use a mirror gate for the generation of both generate and propagate signals, which exhibits a forbidden input signal combination. This "forbidden state" causes an increase in power dissipation due to transient short circuit currents. The effect of the forbidden state was quantified as part of a comparison against the classical prefix operator, based on 64-bit Sklansky adders implemented in a 40-nm CMOS technology. The effects of the forbidden state were found to be well acceptable. The implementation of the adder based on the proposed prefix operator reduces the area by 29% while increasing the power by 13% compared to one based on the classical operator.

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