Novel Full TMR Placement Techniques for High-Speed Radiation Tolerant Digital Integrated Circuits
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This paper presents a novel physical implementation methodology for high-speed Triple Modular Redundant (TMR) digital integrated circuits for harsh radiation environment applications. An improved distributed approach is presented to constrain redundant branches of Triple Modular Redundant (TMR) digital logic cells using repetitive, interleaved micro-floorplans. To optimally constrain the placement of both sequential and combinational cells, the TMR netlist is used to segment the the logic into unrelated groups allowing sharing without compromising reliability. The technique was evaluated in a 65 nm bulk CMOS technology and a comparison is made to conventional methods.
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1995 ◽
Vol 06
(01)
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pp. 163-210
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2004 ◽
Vol 14
(02)
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pp. 367-378
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