Measuring Leakage Power in Nanometer CMOS 6T-SRAM Cells

In deep sub-micro CMOS process, the leakage power is becoming a significant proportion in power dissipation. Hence, estimating the leakage power of CMOS circuits is very important in low-power design. In this paper, an estimation technology for the total leakage power of adiabatic logic circuits by using SPICE is proposed. The basic principle of power estimation for traditional CMOS circuits using SPICE is introduced. According to the energy dissipation characteristic of adiabatic circuits, the estimation technology for leakage power is discussed. Taken as an example, the estimation for total leakage power dissipations of PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits is illustrated using the proposed estimation technology.

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Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2009.2035448 ◽

2011 ◽

Vol 19 (3) ◽

pp. 469-482 ◽

Cited By ~ 13

Author(s):

Ashoka Sathanur ◽

Luca Benini ◽

Alberto Macii ◽

Enrico Macii ◽

Massimo Poncino

Keyword(s):

Power Optimization ◽

Leakage Power ◽

Cmos Circuits ◽

Power Gating ◽

Nanometer Cmos

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P-Type Adiabatic Sequential Circuits for Leakage Reduction of Nanometer Circuits

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.159.155 ◽

2010 ◽

Vol 159 ◽

pp. 155-161

Author(s):

Jin Tao Jiang ◽

Yu Zhang ◽

Jian Ping Hu

Keyword(s):

Power Consumption ◽

Leakage Power ◽

Sequential Circuits ◽

Technology Scaling ◽

Nanometer Cmos ◽

Gate Structure ◽

Adiabatic Logic ◽

Pass Transistor ◽

P Type ◽

Cmos Processes

With rapid technology scaling, the proportion of the leakage power catches up with dynamic power gradually. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. This paper presents adiabatic sequential circuits using P-type complementary pass-transistor adiabatic logic circuit (P-CPAL) to reduce the gate-leakage power dissipations. A practical sequential system with a mode-10 counter is demonstrated using the P-CPAL scheme. All circuits are simulated using HSPICE under 65nm and 90nm CMOS processes. Simulations show that the mode-10 counter using P-CPAL circuits obtains significant improvement in terms of power consumption over the traditional N-type CPAL counterparts.

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Power Dissipation Analysis of Adiabatic Circuits and Active Leakage Power Estimation in Nanometer CMOS Processes

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.121-122.97 ◽

2010 ◽

Vol 121-122 ◽

pp. 97-102 ◽

Cited By ~ 3

Author(s):

Wei Qiang Zhang ◽

Li Su ◽

Li Fang Ye ◽

Jian Ping Hu

Keyword(s):

Power Dissipation ◽

Low Power Design ◽

Logic Circuits ◽

Leakage Power ◽

Nanometer Cmos ◽

Wide Range ◽

Adiabatic Logic ◽

Total Leakage ◽

Pass Transistor ◽

Simulation Results

The leakage dissipations of nano-circuits have become a critical concern. Estimating the leakage power of nano-circuits is very important in low-power design. This paper presents a new estimation technology for the active leakage dissipations of adiabatic logic circuits. Based on the power dissipation models of adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations with additional capacitances on load nodes of the adiabatic circuits using HSPICE simulations. Taken as an example, the estimation for dynamic and active leakage power dissipations of CPAL (Complementary Pass-transistor Adiabatic Logic) circuits is demonstrated using the proposed estimation technology. The simulation results show that the proposed estimation technology can accurately estimate the active leakage dissipations of CPAL circuits with an accepted error over a wide range of frequencies.

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