CMOS High-Speed 1/14 Dynamic Frequency Divider

Author(s):  
Queennie Lim Suan Imm ◽  
Albert Victor Kordesch ◽  
Burhanuddin Yeop Majlis
Author(s):  
T. Ichioka ◽  
K. Tanaka ◽  
T. Saito ◽  
S. Nishi ◽  
M. Akiyama

2013 ◽  
Vol 441 ◽  
pp. 125-128
Author(s):  
Li Fan Wu

A clock-inverter feed-forward toggle flip-flop (CIFF-TFF) based ultra-high-speed 2:1 dynamic frequency divider is designed in a GaAs heterojunction bipolar transistor (HBT) technology with fT of 60 GHz from Win Semiconductors corporation. The co-simulation methodology of electromagnetic field and schematic diagram is utilized in the design. Through tuning the currents in the core and the other parts of the divider separately, the dynamic frequency divider approaches an operating speed of 36 GHz with a power consumption of 162 mW in the core part from a single 6 V supply. The design is currently taped out.


2001 ◽  
Vol 11 (01) ◽  
pp. 35-76 ◽  
Author(s):  
MARTIN WURZER ◽  
THOMAS F. MEISTER ◽  
JOSEF BÖCK ◽  
HERBERT SCHÄFER ◽  
KLAUS AUFINGER ◽  
...  

In this paper we present Si and SiGe bipolar technologies and circuits suited for present and future high-performance communication systems. The silicon bipolar technology described has an implanted base and, without increase in process complexity in comparison to current production technologies, transit frequencies of 52 GHz and maximum oscillation frequencies of 65 GHz are achieved. The transistors of the described epitaxial SiGe-base technologies exhibit transit frequencies of 81 GHz and maximum oscillation frequencies of 95 GHz. Measurement results of circuits realized in these technologies for low power and high-speed applications are presented: a 43 GHz low power dynamic frequency divider, a 23 GHz monolithically integrated oscillator, a 40 Gb/s clock and data (CDR) recovery realized in the pure silicon bipolar technology, and a 53 GHz static frequency divider, a 79 GHz dynamic frequency divider and a 20 GHz/27 mW dual-modulus prescaler in the SiGe technology.


2003 ◽  
Author(s):  
T. Saito ◽  
H.I. Fujishiro ◽  
T. Ichioka ◽  
K. Tanaka ◽  
S. Nishi ◽  
...  

Author(s):  
Jidan Al-Eryani ◽  
Herbert Knapp ◽  
Hao Li ◽  
Klaus Aufinger ◽  
Jonas Wursthorn ◽  
...  

1994 ◽  
Vol 05 (03) ◽  
pp. 349-379 ◽  
Author(s):  
T. ISHIBASHI ◽  
Y. YAMAUCHI ◽  
E. SANO ◽  
H. NAKAJIMA ◽  
Y. MATSUOKA

We describe the design, fabrication and application of ballistic collection transistors (BCTs) in which electron velocity overshoot is introduced in the collector of a GaAs-based heterojunction bipolar transistor. The guideline for the BCT design is the effective confinement of electrons to the Γ-valley, as simulated by Monte Carlo analysis, and the control of electron energy is accomplished basically with an i-p+-n+ doping profile. Microwave characterization demonstrates the existence of significant overshoot and cutoff frequencies higher than 100 GHz at collector current densities in the mid 104 A/cm 2 range for a typical BCT structure. Some high speed integrated circuits implemented with BCTs include a selector circuit that operates at bit rates up to 40 Gb/s, a dynamic frequency divider with divide-by-four function up to 50 GHz and a broadband preamplifier having an S21 bandwidth as high as 40 GHz.


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