High-Speed GaAs 1/8 Dynamic Frequency Divider Stabilized for Supply Voltage Fluctuation and its Phase Noise Characteristics

Abstract This paper introduces a design of a high-speed programmable multi-modulus divider (MMD) based on 65nm CMOS process. The design adopts the cascade structure of 7 level 2/3 frequency dividers, and expands the frequency division range by adjusting the number of cascade stages, so as to achieve a continuous frequency division ratio of 16 to 255. Among them, the first level 2/3 frequency divider adopts the D flip-flop design of CML (current mode logic) structure, the second level 2/3 frequency divider adopts the D flip-flop design of E-TSPC (extended true-single-phase-clock) structure. The whole circuit realizes the working frequency range of 13∼18GHz high frequency and large bandwidth. This design has completed layout drawing and parasitic parameter extraction simulation. The simulation results show that the operating frequency range of the circuit can reach 13∼18GHz. When the input signal is 18GHz and the frequency division ratio is 255, the phase noise is about -135dBc/Hz@1kHz. It has the advantages of high frequency, large bandwidth, and low phase noise.

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An ultra-high speed DCFL dynamic frequency divider

10.1109/mcs.1989.37263 ◽

2003 ◽

Cited By ~ 4

Author(s):

T. Ichioka ◽

K. Tanaka ◽

T. Saito ◽

S. Nishi ◽

M. Akiyama

Keyword(s):

High Speed ◽

Frequency Divider ◽

Ultra High Speed ◽

Dynamic Frequency

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Effects of Hot-Carrier Stress on the RF Performance of a 0.18-μm MOS Divide-by-4 LC Injection-Locked Frequency Divider

Fluctuation and Noise Letters ◽

10.1142/s0219477514500096 ◽

2014 ◽

Vol 13 (02) ◽

pp. 1450009

Author(s):

Sheng-Lyang Jang ◽

Tsung-Chao Fu

Keyword(s):

Phase Noise ◽

Frequency Tuning ◽

Supply Voltage ◽

Direct Injection ◽

Frequency Divider ◽

External Signal ◽

Cmos Process ◽

Hot Carrier ◽

Locking Range ◽

Hot Carrier Stress

The effect of ac hot-carrier stress on the performance of a wide locking range divide-by-4 injection-locked frequency divider (ILFD) is investigated. The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD uses direct injection MOSFETs for coupling external signal to the resonators. Radio frequency (RF) circuit parameters such as oscillation frequency, tuning range, phase noise, and locking range before and after RF stress at an elevated supply voltage for 5 h have been examined by experiment. The measured locking range, operation range and phase noise after RF stress shows significant degradation from the fresh circuit condition.

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A 36 GHz CIFF-TFF Dynamic Frequency Divider Using GaAs HBTs

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.441.125 ◽

2013 ◽

Vol 441 ◽

pp. 125-128

Author(s):

Li Fan Wu

Keyword(s):

High Speed ◽

Heterojunction Bipolar Transistor ◽

Frequency Divider ◽

Schematic Diagram ◽

60 Ghz ◽

Flip Flop ◽

Simulation Methodology ◽

The Core ◽

Core Part ◽

Dynamic Frequency

A clock-inverter feed-forward toggle flip-flop (CIFF-TFF) based ultra-high-speed 2:1 dynamic frequency divider is designed in a GaAs heterojunction bipolar transistor (HBT) technology with fT of 60 GHz from Win Semiconductors corporation. The co-simulation methodology of electromagnetic field and schematic diagram is utilized in the design. Through tuning the currents in the core and the other parts of the divider separately, the dynamic frequency divider approaches an operating speed of 36 GHz with a power consumption of 162 mW in the core part from a single 6 V supply. The design is currently taped out.

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An Ultra-High-Speed GaAs Prescaler Using a Dynamic Frequency Divider

IEEE Transactions on Microwave Theory and Techniques ◽

10.1109/tmtt.1987.1133587 ◽

1987 ◽

Vol 35 (1) ◽

pp. 9-13 ◽

Cited By ~ 5

Author(s):

K. Osafune ◽

K. Ohwada

Keyword(s):

High Speed ◽

Frequency Divider ◽

Ultra High Speed ◽

Dynamic Frequency

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HIGH-PERFORMANCE Si and SiGe BIPOLAR TECHNOLOGIES AND CIRCUITS

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156401000782 ◽

2001 ◽

Vol 11 (01) ◽

pp. 35-76 ◽

Cited By ~ 1

Author(s):

MARTIN WURZER ◽

THOMAS F. MEISTER ◽

JOSEF BÖCK ◽

HERBERT SCHÄFER ◽

KLAUS AUFINGER ◽

...

Keyword(s):

Low Power ◽

Communication Systems ◽

High Speed ◽

High Performance ◽

Frequency Divider ◽

Pure Silicon ◽

Bipolar Technology ◽

Silicon Bipolar Technology ◽

Oscillation Frequencies ◽

Dynamic Frequency

In this paper we present Si and SiGe bipolar technologies and circuits suited for present and future high-performance communication systems. The silicon bipolar technology described has an implanted base and, without increase in process complexity in comparison to current production technologies, transit frequencies of 52 GHz and maximum oscillation frequencies of 65 GHz are achieved. The transistors of the described epitaxial SiGe-base technologies exhibit transit frequencies of 81 GHz and maximum oscillation frequencies of 95 GHz. Measurement results of circuits realized in these technologies for low power and high-speed applications are presented: a 43 GHz low power dynamic frequency divider, a 23 GHz monolithically integrated oscillator, a 40 Gb/s clock and data (CDR) recovery realized in the pure silicon bipolar technology, and a 53 GHz static frequency divider, a 79 GHz dynamic frequency divider and a 20 GHz/27 mW dual-modulus prescaler in the SiGe technology.

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