A Continuous-time Hierarchical Field Programmable Analogue Array for Rapid Prototyping and Hierarchical Approach to Analogue Systems Design

2005 ◽  
Author(s):  
David Varghese ◽  
J. N. Ross
Keyword(s):  
Rapid Prototyping ◽  
Continuous Time ◽  
Systems Design ◽  
Hierarchical Approach ◽  
Field Programmable

Rapid prototyping of algorithmic A/D converters based on FPAA devices

2013 ◽  
Vol 61 (3) ◽  
pp. 691-696 ◽  
Author(s):  
R. Suszynski ◽  
K. Wawryn
Keyword(s):  
Rapid Prototyping ◽  
Sinusoidal Signal ◽  
Digital Converter ◽  
Mixed Signal ◽  
Analog Digital Converter ◽  
Signal Systems ◽  
Programmable Analog ◽  
Field Programmable ◽  
Field Programmable Analog Array

Abstract A rapid prototyping method for designing mixed signal systems has been presented in the paper. The method is based on implementation of the field programmable analog array (FPAA) to configure and reconfigure mixed signal systems. A serial algorithmic analog digital converter has been used as an example. Three converter architectures have been selected and implemented FPAA device. To verify and illustrate converters operation and prototyping capabilities, implemented converters have been excited by a sinusoidal signal. Analog sinusoidal excitations, digital responses and sinusoidal waveforms after reconstruction are presented.

Engineering and Technology Based on Rapid Prototyping

2015 ◽  
Vol 770 ◽  
pp. 622-627 ◽  
Author(s):  
A.A. Saprikin ◽  
E.A. Ibragimov ◽  
E.V. Babakova
Keyword(s):  
Product Development ◽  
Rapid Prototyping ◽  
Systems Design ◽  
Design And Technology ◽  
Solid Model ◽  
Layer Deposition ◽  
Automation Systems ◽  
Engineering And Technology ◽  
Cad Cam ◽  
Technology Cad

In the process of design and product development, prototyping model is an important step to finalize the product. Rapid Prototyping (RP) is a technology of product synthesis layer deposition material. The method was developed in the early 1980s as a consequence of the enormous growth of automation systems design and technology (CAD / CAM). The prototype of a complex solid model to determine the final appearance of the product, evaluate the assemblability of products, etc.

scholarly journals Eine FPAA-Architektur zur rekonfigurierbaren Instantiierung von zeitkontinuierlichen Analogfiltern

2005 ◽  
Vol 3 ◽  
pp. 371-375 ◽  
Author(s):  
J. Becker ◽  
Y. Manoli
Keyword(s):  
Continuous Time ◽  
Wird Eine ◽  
Programmable Analog ◽  
Field Programmable ◽  
Field Programmable Analog Arrays ◽  
Analog Blocks ◽  
Analog Arrays ◽  
Butterworth Filters

Abstract. Im Folgenden wird eine neue Methodik von FPAAs (Field Programmable Analog Arrays) gezeigt, die speziell für die Instantiierung von zeitkontinuierlichen (continuous-time, CT) Analogfiltern in Hardware entwickelt wurde. Die Chiptopologie beinhaltet 17 digital konfigurierbare analoge Blöcke (configurable analog blocks, CABs), die durch ein hexagonales Netzwerk miteinander verbunden sind. Jeder CAB ist aus einstellbaren Gm-C Integratoren aufgebaut, welche das analoge Signal sowohl formen und seinen Weg durch die Matrix festlegen, gleichzeitig aber auch die Grundbausteine für zeitkontinuierliche Hochfrequenzfilter darstellen. Intelligente Pufferspeicher für die Ein-/Ausgänge (IO-buffer) garantieren die Rekonfigurierung der Matrix mit minimaler Störung des kontinuierlichen Analogsignals. Die Architektur wird als Hardwareplattform für beliebige Schaltungen, welche aus einer gegebenen Anzahl an Gm-C-Zellen bestehen, eingeführt und verifiziert bevor eine exemplarische Instantiierung eines Butterworth Filters 4. Ordnung in Biquad Anordnung gezeigt wird.

scholarly journals BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications Applications

2018 ◽  
Vol 7 (1) ◽  
pp. 1
Author(s):  
M. Parvathi ◽  
N. Vasantha ◽  
K. Satya Prasad
Keyword(s):  
Systems Design ◽  
Digital Signal ◽  
Low Area ◽  
Gate Arrays ◽  
Current Limit ◽  
Maximum Current ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Layout Area ◽  
Signal Processors

One of the important block of BIST controller is LFSR and the speed with which BIST operates depends on LFSR systems design. There are methods in implementing LFSR using field programmable gate arrays (FPGAs) or digital signal processors (DSPs). BIST controller system speed is then limited to FPGAs and DSPs, which may influence other parameters such as overall area, maximum current, limit and power dissipation. This paper proposes a technique to achieve an efficient BIST controller by redesigning LFSR using GDI based D flip-flops that resulted with low area and low current capabilities. This paper presents three different techniques for implementing flip-flops for an efficient LFSR so that the layout area will be minimized as well as the maximum current drawn will be lower.

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