Investigation of Idle Running and Short-Circuit Performance Improvement for an Asynchronous Traction Motor

Author(s):  
Nicolae Raluca-Cristina ◽  
Vlad Ion ◽  
Nicolae Marian-Stefan ◽  
Enache Sorin
2019 ◽  
Vol 963 ◽  
pp. 797-800 ◽  
Author(s):  
Ajit Kanale ◽  
Ki Jeong Han ◽  
B. Jayant Baliga ◽  
Subhashish Bhattacharya

The high-temperature switching performance of a 1.2kV SiC JBSFET is compared with a 1.2kV SiC MOSFET using a clamped inductive load switching circuit representing typical H-bridge inverters. The switching losses of the SiC MOSFET are also evaluated with a SiC JBS Diode connected antiparallel to it. Measurements are made with different high-side and low-side device options across a range of case temperatures. The JBSFET is observed to display a reduction in peak turn-on current – up to 18.9% at 150°C and a significantly lesser turn-on switching loss – up to 46.6% at 150°C, compared to the SiC MOSFET.


2021 ◽  
Author(s):  
V. Sreeram ◽  
M. Rajkumar ◽  
S. S. Reddy ◽  
T. Gurudev ◽  
Maroti

2020 ◽  
Vol 1004 ◽  
pp. 770-775
Author(s):  
Rina Tanaka ◽  
Katsutoshi Sugawara ◽  
Yutaka Fukui ◽  
Hideyuki Hatta ◽  
Hidenori Koketsu ◽  
...  

Gate oxide reliability of a trench-gate SiC MOSFET can be improved by incorporating a gate protection structure, but the resulting parasitic JFET resistance is one major drawback. For reduction of on-resistance, a new method of localized high-concentration n-type doping in JFET regions (JD) is developed. Utilizing process and device simulation by TCAD, the optimal condition of JD that enables maximum device performance is derived. By fabricating a device with the optimal JD structure, the on-resistance is successfully reduced by 25% compared to a conventional device without JD, while maintaining the withstand voltage and the gate oxide electric field at the same level. As a result, a device exhibiting a specific on-resistance of 1.84 mΩcm2 and a breakdown voltage of 1560 V is obtained. The optimal JD structure maintains the short-circuit safe operation area comparable to that for the structure without JD. Thus, by reducing the JFET resistance while minimizing effects on other characteristics, localized JD is shown to be an effective means of realizing a reliable, low-resistance SiC power device.


2020 ◽  
Vol 1004 ◽  
pp. 783-788
Author(s):  
Ki Jeong Han ◽  
Ajit Kanale ◽  
B. Jayant Baliga ◽  
Subhashish Bhattacharya

The electrical characteristics of the 1.2-kV rated 4H-SiC accumulation-channel split-gate octagonal cell MOSFET (SG-OCTFET) are experimentally compared with linear, square, hexagonal, octagonal, and compact-octagonal cell topologies. The specific on-resistance of the SG-OCTFET is 52% larger than the conventional linear cell topology. However, the SG-OCTFET has: (i) high-frequency figure-of-merit HFFOM[Ron×Cgd] 9.4×, 6.1×, 2.6×, 2.0×, and 1.8× superior to the square, hex, linear, octagonal, and compact-octagonal cells; (ii) fastest switching performance among all cell topologies, with 26% smaller switching energy loss than the conventional linear cell topology; and (iii) short circuit capability 1.5× longer than the conventional linear cell topology. The SG-OCTFET device is therefore an optimum candidate for high frequency applications of SiC MOSFETs.


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