Low Insertion-loss Stacked Transformers Using Tapered Spirals for High Performance RFICs

Author(s):  
Venkata Narayana Rao Vanukuru
2020 ◽  
Vol 2020 (1) ◽  
pp. 000211-000216
Author(s):  
Tatsushi Hayashi ◽  
Po Yu Lin ◽  
Ryoichi Watanabe ◽  
Seiko Ichikawa

Abstract With IP traffic increasing by 10-fold over the last decade, together with limitation and cost increase due to shrinking semiconductor nodes have led to requiring technological breakthrough in the packaging of semiconductor devices especially those used in high performance computing (HPC).This increase in IP traffic has led to requirement for higher data speed transmission in these devices, and consequently packaging technologies that enable those solutions such as 2.5D packaging utilizing silicon interposers. Furthermore, in recent years, increasing number of dies are placed in a single package for these devices thereby making the size of silicon interposers larger. Thus, the design of organic substrates used in these devices, are also becoming ever complex often with multiple layers with long trace lengths for routing increased number of IOs and allowing for power and signal control management. In order to facilitate the high speed data transmission requirement with longer trace lengths, stable low insertion loss design of organic substrates are becoming significantly important even when devices are exposed at elevated humidity or higher temperatures due to surrounding environment or from dies heating. Additionally, as silicon interposers are increasing in size, preventing stress build-up, which can cause cracking between the interposer and the organic substrate, is also becoming paramount. These requirements have led to innovative materials to be developed to enable organic substrates to have these properties. In this paper, we present a new dielectric build-up material for use in advanced organic substrates, by combining newly developed original resin with existing formulation technology that meet these criteria of enabling lower insertion loss with design that reduces deterioration even at elevated humidity and temperature, and furthermore having high crack resistance during temperature cycle testing.


2016 ◽  
Vol 88 (2) ◽  
pp. 1089-1098 ◽  
Author(s):  
Mohammad A.S. Bhuiyan ◽  
Yeoh Zijie ◽  
Jae S. Yu ◽  
Mamun B.I. Reaz ◽  
Noorfazila Kamal ◽  
...  

Modern Radio Frequency (RF) transceivers cannot be imagined without high-performance (Transmit/Receive) T/R switch. Available T/R switches suffer mainly due to the lack of good trade-off among the performance parameters, where high isolation and low insertion loss are very essential. In this study, a T/R switch with high isolation and low insertion loss performance has been designed by using Silterra 0.13µm CMOS process for 2.4GHz ISM band RF transceivers. Transistor aspect ratio optimization, proper gate bias resistance, resistive body floating and active inductor-based parallel resonance techniques have been implemented to achieve better trade-off. The proposed T/R switch exhibits 0.85dB insertion loss and 45.17dB isolation in both transmit and receive modes. Moreover, it shows very competitive values of power handling capability (P1dB) and linearity (IIP3) which are 11.35dBm and 19.60dBm, respectively. Due to avoiding bulky inductor and capacitor, the proposed active inductor-based T/R switch became highly compact occupying only 0.003mm2 of silicon space; which will further trim down the total cost of the transceiver. Therefore, the proposed active inductor-based T/R switch in 0.13µm CMOS process will be highly useful for the electronic industries where low-power, high-performance and compactness of devices are the crucial concerns.


2013 ◽  
Vol 798-799 ◽  
pp. 520-525 ◽  
Author(s):  
Cheng Peng Liu ◽  
Jian Gang Shi ◽  
Zheng Rong He ◽  
Wei Zou

a novel configuration for a novel ultra wideband switch is presented in this paper. This switch using 0.5um GaAs process in ADS2008 simulator. Switch should be designed to trade-off insertion loss, isolation, bandwidth, and return loss. The aims of design are to provide low insertion loss along with high isolation. The design using integration inductor and resistor in parallel, and this switch exhibits high performance: over DC-10.6GHz, insertion loss is lower than-1.624dB; the ripple variation of insertion loss is less than ±0.25dB; The isolation is lower than-51.336dB; input return loss is lower than-16.402dB; on state, output return loss is lower than-15.919dB; off state, output return loss is lower than-18.294dB; on and off time are less than 4ns.


2020 ◽  
Vol 8 (1) ◽  
pp. 1-4
Author(s):  
Sayed M. Hosseini ◽  
Abbas Rezaei

branch-line microstrip coupler is designed and fabricated in this paper. The proposed coupler operates at 3 GHz, which is suitable for WiMAX applications. The designed coupler has a high performance, that is, a low phase difference of 0.49°, low insertion loss, good coupling factor, and good isolation better than −30 dB. Another advantage of the designed coupler is its novel geometrical structure based on integrating the semi-circular and step impedance cells. The design process is based on introducing and analyzing an equivalent LC model to improve impedance matching and reduce losses. To verify the design process, the designed coupler is fabricated, where a good agreement between the simulation result and measurement is achieved.


Author(s):  
Aparna B. Barbadekar ◽  
Pradeep M. Patil

Abstract The paper proposes a system consisting of novel programmable system on chip (PSoC)-controlled phase shifters which in turn guides the beam of an antenna array attached to it. Four antennae forming an array receive individual inputs from the programmable phase shifters (IC 2484). The input to the PSoC-based phase shifter is provided from an optimized 1:4 Wilkinson power divider. The antenna consists of an inverted L-shaped dipole on the front and two mirrored inverted L-shaped dipoles mounted on a rectangular conductive structure on the back which resonates in the ISM/Wi-Fi band (2.40–2.48 GHz). The power divider is designed to provide the feed to the phase shifter using a beamforming network while ensuring good isolation among the ports. The power divider has measured S11, S21, S31, S41, and S51 to be −14, −6.25, −6.31, −6.28, and −6.31 dB, respectively at a frequency of 2.45 GHz. The ingenious controller is designed in-house using a PSoC microcontroller to regulate the control voltage of individual phase shifter IC and generate progressive phase shifts. To validate the calibration of the in-house designed control circuit, the phased array is simulated using $s_p^2$ touchstone file of IC 2484. This designed control circuit exhibits low insertion loss close to −8.5 dB, voltage standing wave ratio of 1.58:1, and reflection coefficient (S11) is −14.36 dB at 2.45 GHz. Low insertion loss variations confirm that the phased-array antenna gives equal amplitude and phase. The beamforming radiation patterns for different scan angles (30, 60, and 90°) for experimental and simulated phased-array antenna are matched accurately showing the accuracy of the control circuit designed. The average experimental and simulated gain is 13.03 and 13.48 dBi respectively. The in-house designed controller overcomes the primary limitations associated with the present electromechanical phased array such as cost weight, size, power consumption, and complexity in design which limits the use of a phased array to military applications only. The current study with novel design and enhanced performance makes the system worthy of the practical use of phased-array antennas for common society at large.


Optik ◽  
2019 ◽  
Vol 194 ◽  
pp. 163069 ◽  
Author(s):  
Kawsar Ahmed ◽  
Md. Ferdous ◽  
Md. Nazmul Hossen ◽  
Bikash Kumar Paul ◽  
I.S. Amiri ◽  
...  

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