Analysis of the latch-up process and current filamentation in high-voltage trench-IGBT cell arrays

2013 ◽  
Author(s):  
C. Toechterle ◽  
F. Pfirsch ◽  
C. Sandow ◽  
G. Wachutka
Keyword(s):  
High Voltage ◽  
Cell Arrays ◽  
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A Novel High Latch-Up Immunity Electrostatic Discharge Protection Device for Power Rail in High-Voltage ICs

2016 ◽  
Vol 16 (2) ◽  
pp. 266-268
Author(s):  
Chunwei Zhang ◽  
Siyang Liu ◽  
Kaikai Xu ◽  
Jiaxing Wei ◽  
Ran Ye ◽  
...  
Keyword(s):  
High Voltage ◽  
Electrostatic Discharge ◽  
Protection Device ◽  
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An Optimization Design in the HV nLDMOS by Taguchi Method

2012 ◽  
Vol 482-484 ◽  
pp. 81-84 ◽  
Author(s):  
Shen Li Chen ◽  
Tzung Shian Wu ◽  
Yun Ru Chen ◽  
Hung Wei Chen ◽  
Chun Hsing Shih ◽  
...  
Keyword(s):  
Taguchi Method ◽  
High Voltage ◽  
Optimization Design ◽  
Applied Model ◽  
Adaptive Adjustment ◽  
Buried Layer ◽  
The Times ◽  
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This paper applied the Taguchi method to simulate the latch-up effect of nLDMOS to achieve an optimization design. The applied model is for an nLDMOS structure with high voltage well plus the adaptive (adjustment) layers of source & drain, and an N-type buried layer. Although the methods we could choose is abundant, we hope to effectively obtain the data which is useful for statistics in order to judge the correct characteristic of parameters. We applied the Taguchi method to perform an optimization in the paper. There are six parameters with two levels in this work, so we choose the Taguchi table to be L8(27). By this way, it can decrease the times of experiment much effectively.

Influence of a Deep NBL Structure on ESD/Latch-Up Immunities in the Power Device nLDMOS

2013 ◽  
Vol 732-733 ◽  
pp. 1207-1211
Author(s):  
Shen Li Chen ◽  
Tzung Shian Wu
Keyword(s):  
Power Electronics ◽  
High Voltage ◽  
Power Device ◽  
Esd Protection ◽  
Buried Layer ◽  
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In this paper, we propose a novel high-voltage (HV) nLDMOS transistor with a small Ron resistance, low trigger voltage (Vt1) and high holding voltage (Vh) characteristics. Here, we introduce a deep N+-buried-layer (NBL) into this HV nLDMOS to evaluate the ESD/latch-up (LU) parameters variation. These electric snapback parameters affect the reliability of proposed device and its performance. Eventually, we expect this proposed HV stucture processed better characteristic behaviors, which can be applied to the power electronics and ESD protection application of HV ICs.

Analysis of triggering behaviour of high voltage CMOS LDMOS clamps and SCRs during ESD induced latch-up

2006 ◽  
Vol 46 (9-11) ◽  
pp. 1591-1596 ◽  
Author(s):  
M. Heer ◽  
V. Dubec ◽  
S. Bychikhin ◽  
D. Pogany ◽  
E. Gornik ◽  
...  
Keyword(s):  
High Voltage ◽  
Latch Up

TC-LIGBTs on the Thin SoI Layer for the High Voltage Monolithic ICs With High Current Density and Latch-Up Immunity

2014 ◽  
Vol 61 (11) ◽  
pp. 3814-3820 ◽  
Author(s):  
Jing Zhu ◽  
Weifeng Sun ◽  
Weinan Dai ◽  
Long Zhang ◽  
Shenli Lu ◽  
...  
Keyword(s):  
High Voltage ◽  
Current Density ◽  
High Current Density ◽  
High Current ◽  
Latch Up
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