Effect of IC package on radiated susceptibility of board level interconnection

2015 ◽  
Author(s):  
Fatemeh Vafaee Zonouz ◽  
Nasser Masoumi ◽  
Milad Mehri
Keyword(s):  
Board Level ◽  
Ic Package

Various Levels of Drop Analysis for BGA in Mobile Phones

2007 ◽  
Author(s):  
Takayoshi Katahira ◽  
Masato Fujita ◽  
Tsuyoki Shibata ◽  
Masaki Shiratori ◽  
Qiang Yu
Keyword(s):  
Mobile Phones ◽  
High Speed ◽  
Dielectric Materials ◽  
System Level ◽  
Detailed Model ◽  
Multiple Devices ◽  
Micro Level ◽  
Orthotropic Properties ◽  
Board Level ◽  
Ic Package

To final product quality of mobile phones, key reliability requirements are drop, bend and thermal cycling. Especially in terms of IC-device, drop reliability is the most significant of the three, and also difficult to optimize since it is a dynamic phenomenon in high speed and drop reliability is influenced by 1) system-level factors, 2) board-level and 3) micro-level. In this paper, system-level is defined as phone-level drop, specifically simplified mono-block phone including multiple devices on PWB. System-level enables to evaluate various factors, drop height, drop directions, materials to drop on, phone weight and phone mechanics. Board-level indicates IC-package, PWB and solder joints connecting in between. The board-assembled PWB is fixed onto fixture at 2∼6 points. Drop direction is flat drop only. This paper defines micro level as more detailed model than board level. PWB is modeled as composite structure consisting of dielectric materials with orthotropic properties, copper layers and micro via. IC-package is modeled as well. System level drop shows significant differences in drop directions and also the interactions between drop direction and component location. Micro level simulation results are well-correlative with experimental in failure mode. This paper will discuss overview of 3 levels of drop modeling and will focus on micro level and system level analysis in conjunction with board level.

Board Level Drop Impact—Fundamental and Parametric Analysis

2005 ◽  
Vol 127 (4) ◽  
pp. 496-502 ◽  
Author(s):  
E. H. Wong ◽  
Y-W Mai ◽  
S. K. W. Seah
Keyword(s):  
Static Analysis ◽  
Bending Moment ◽  
Drop Impact ◽  
Computational Effort ◽  
Temperature Cycling ◽  
Mass System ◽  
Pcb Assembly ◽  
Impact Reliability ◽  
Board Level ◽  
Ic Package

A fundamental understanding of the dynamics of the PCB assembly when subjected to a half-sine acceleration has also been obtained through analyzing the PCB as a spring mass system, a beam, and a plate, respectively. The magnitude of stresses in solder interconnection due to flexing of the PCB is two orders higher than the magnitude of the stresses induced by acceleration and inertia loading the IC package. By ignoring the inertia loading, computational effort to evaluate the interconnection stresses due to PCB flexing can be reduced significantly via a two-step dynamic-static analysis. The dynamic analysis is first performed to evaluate the PCB bending moment adjacent the package, and is followed by a static analysis where the PCB bending moment is applied around the package. Parametric studies performed suggest a fundamental difference in designing for drop impact and designing for temperature cycling. The well-known design rules for temperature cycling—minimizing package length and maximizing interconnection standoff—does not work for drop impact. Instead, drop impact reliability can be enhanced by increasing the interconnection diameter, reducing the modulus of the interconnection materials, reducing the span of the PCB, or using either a very thin or a very thick PCB.

Acoustic microscopy techniques for the inspection of integrated circuit devices and packages

1992 ◽  
Vol 50 (2) ◽  
pp. 966-967
Author(s):  
Thomas M. Moore
Keyword(s):  
Integrated Circuit ◽  
Acoustic Microscopy ◽  
Hybrid Technique ◽  
Frequency Scanning ◽  
Ic Packaging ◽  
Ic Package ◽  
Microscopy Techniques ◽  
Ic Package Inspection ◽  
Pulse Echo ◽  
Scanning Acoustic Microscope

In the last decade, a variety of characterization techniques based on acoustic phenomena have come into widespread use. Characteristics of matter waves such as their ability to penetrate optically opaque solids and produce image contrast based on acoustic impedance differences have made these techniques attractive to semiconductor and integrated circuit (IC) packaging researchers.These techniques can be divided into two groups. The first group includes techniques primarily applied to IC package inspection which take advantage of the ability of ultrasound to penetrate deeply and nondestructively through optically opaque solids. C-mode Acoustic Microscopy (C-AM) is a recently developed hybrid technique which combines the narrow-band pulse-echo piezotransducers of conventional C-scan recording with the precision scanning and sophisticated signal analysis capabilities normally associated with the high frequency Scanning Acoustic Microscope (SAM). A single piezotransducer is scanned over the sample and both transmits acoustic pulses into the sample and receives acoustic echo signals from the sample.

Failure Localization of Intermittent Short Failures Caused by Vertical Conductive Anodic Filament Formation

2014 ◽  
Author(s):  
Daniel Nuez ◽  
Phoumra Tan
Keyword(s):  
Glass Fibers ◽  
Vertical Plane ◽  
Axis Formation ◽  
Metal Trace ◽  
Conductive Anodic Filament ◽  
Plated Through Hole ◽  
Voltage Gradients ◽  
Ic Package ◽  
Through Hole ◽  
Failure Localization

Abstract Conductive anodic filament (CAF) formation is a mechanism caused by an electrochemical migration of metals from a metal trace in ICs or in PCBs. This is commonly caused by the moisture build-up in the affected metal terminals in an IC package or PC board caused by critical temperature, high humidity and high voltage gradients conditions. This phenomenon is known to have caused catastrophic field failures on various OEMs electronic components in the past [1,7]. Most published articles on CAF described the formation of the filament in a lateral formation through the glass fiber interfaces between two adjacent metal planes [1-6, 8-12]. One common example is the CAF formation seen between PTH (Plated through Hole) in the laminated substrate with two different potentials causing shorts [1-6, 8-12]. In this paper, the Cu filament grows in a vertical fashion (z-axis formation) creating a vertical plane shorts between the upper and lower metal terminals in a laminated IC package substrate. The copper growth migration does not follow the fiber strands laterally or vertically through them. Instead, it grows through the stress created gaps between the impregnated carbon epoxy fillers from the upper metal trace to the lower metal trace with two different potentials, between the glass fibers. This vertical CAF mechanism creates a low resistive short that was sometimes found to be intermittent in nature. This paper presents some successful failure analysis approaches used to isolate and detect the failure locations for this type of failing devices. This paper also exposes the unique physical appearance of the vertical CAF formation.

Advanced Acoustic Micro Imaging Applications: Deciphering Multiple Acoustic Echoes and Reflections

2004 ◽  
Author(s):  
Andrew J. Komrowski ◽  
Luis A. Curiel ◽  
Daniel J. D. Sullivan ◽  
Quang Nguyen ◽  
Lisa Logan-Willams
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
New Technologies ◽  
Electronic Packages ◽  
Advanced Packaging ◽  
Ic Package ◽  
Non Destructive

Abstract The acquisition of reliable Acoustic Micro Images (AMI) are an essential non-destructive step in the Failure Analysis (FA) of electronic packages. Advanced packaging and new IC materials present challenges to the collection of reliable AMI signals. The AMI is complicated due to new technologies that utilize an increasing number of interfaces in ICs and packages. We present two case studies in which it is necessary to decipher the acoustic echoes from the signals generated by the interface of interest in order to acquire trustworthy information about the IC package.

In Situ Removal of Polyimide Layer Using Modified Decapsulator

2009 ◽  
Author(s):  
C. Ramachandra ◽  
B.M. Sweety ◽  
U.G. Chandan ◽  
D. Jaypal ◽  
Sarat Kumar Dash ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Analysis Techniques ◽  
Alternative Method ◽  
Ic Package ◽  
Polyimide Layer

Abstract Removal of polyimide layer after decapsulation of IC package is essential for many of the failure analysis techniques. An alternative method for polyimide removal is described in this paper. The method suggests appropriate modification of dual acid decapsulation system for this purpose. Device integrity is verified after removal of polyimide layer. This method becomes promising for devices which are sensitive / vulnerable for exposure to plasma.

Failure Localization in a Multistage S-Band Power Amplifier

2016 ◽  
Author(s):  
Clarence Rebello ◽  
Ted Kolasa ◽  
Parag Modi
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Fault Tree ◽  
Root Cause ◽  
Failure Investigation ◽  
Band Power ◽  
Cause Of Failure ◽  
Design Materials ◽  
Board Level ◽  
Failure Localization

Abstract During the search for the root cause of a board level failure, all aspects of the product must be revisited and investigated. These aspects encompass design, materials, and workmanship. In this discussion, the failure investigation involved an S-Band Power Amplifier assembly exhibiting abnormally low RF output power where initial troubleshooting did not provide a clear cause of failure. A detailed fault tree drove investigations that narrowed the focus to a few possible root causes. However, as the investigation progressed, multiple contributors were eventually discovered, some that were not initially considered.

In-Situ Mechanical Sample Preparation of Selected Sites and Components on Large Modules and Boards

2016 ◽  
Author(s):  
Jim Colvin ◽  
Timothy Hazeldine ◽  
Heenal Patel
Keyword(s):  
Sample Preparation ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Tilt Table ◽  
Standard Requirement ◽  
Open Design ◽  
Bga Packages ◽  
Silicon Thickness ◽  
Board Level

Abstract The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.

3D Integrated Power—A Discrete Perspective

2015 ◽  
Author(s):  
Ian Kearney ◽  
Stephen Brink
Keyword(s):  
Heat Dissipation ◽  
Automatic Test Equipment ◽  
Systematic Analysis ◽  
Power Mosfet ◽  
Root Cause ◽  
Industry Standard ◽  
Bona Fide ◽  
Process Issue ◽  
Board Level ◽  
3D Package

Abstract The shift in power conversion and power management applications to thick copper clip technologies and thinner silicon dies enable high-current connections (overcoming limitations of common wire bond) and enhance the heat dissipation properties of System-in-Package solutions. Powerstage innovation integrates enhanced gate drivers with two MOSFETs combining vertical current flow with a lateral power MOSFET. It provides a low on-resistance and requires an extremely low gate charge with industry-standard package outlines - a combination not previously possible with existing silicon platforms. These advancements in both silicon and 3D Multi-Chip- Module packaging complexity present multifaceted challenges to the failure analyst. The various height levels and assembly interfaces can be difficult to deprocess while maintaining all the critical evidence. Further complicating failure isolation within the system is the integration of multiple chips, which can lead to false positives. Most importantly, the discrete MOSFET all too often gets overlooked as just a simple threeterminal device leading to incorrect deductions in determining true root cause. This paper presents the discrete power MOSFET perspective amidst the competing forces of the system-to-board-level failure analysis. It underlines the requirement for diligent analysis at every step and the importance as an analyst to contest the conflicting assumptions of challenging customers. Automatic Test Equipment (ATE) data-logs reported elevated power MOSFET leakage. Initial assumptions believed a MOSFET silicon process issue existed. Through methodical anamnesis and systematic analysis, the true failure was correctly isolated and the power MOSFET vindicated. The authors emphasize the importance of investigating all available evidence, from a macro to micro 3D package perspective, to achieve the bona fide path forward and true root cause.

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