An integrated fractional-N frequency synthesizer for software-defined radio applications

2010 ◽  
Author(s):  
Sabbir A. Osmany ◽  
Frank Herzel ◽  
J. Christoph Scheytt
Keyword(s):  
Software Defined Radio ◽  
Frequency Synthesizer

A 0.4–6-GHz Frequency Synthesizer Using Dual-Mode VCO for Software-Defined Radio

2013 ◽  
Vol 61 (2) ◽  
pp. 848-859 ◽  
Author(s):  
Jin Zhou ◽  
Wei Li ◽  
Deping Huang ◽  
Chen Lian ◽  
Ning Li ◽  
...  
Keyword(s):  
Software Defined Radio ◽  
Frequency Synthesizer ◽  
Dual Mode

Wideband fraction-N frequency synthesizer design for software-defined radio

WAMICON 2013 ◽  
2013 ◽  
Author(s):  
Jinghong Chen ◽  
Deping Huang ◽  
Wei Li ◽  
Jin Zou ◽  
Changzhi Li
Keyword(s):  
Software Defined Radio ◽  
Frequency Synthesizer

scholarly journals A 0.1-2 GHZ LOW POWER FOLDED RF FRONT-END WITH MERGED LNA AND MIXER FOR SOFTWARE-DEFINED RADIO APPLICATIONS

2013 ◽  
pp. 289-292
Author(s):  
MANJULA. K ◽  
PRATHIBHA. S. K
Keyword(s):  
Low Power ◽  
Software Defined Radio ◽  
Frequency Synthesizer ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Power Performance ◽  
Front End ◽  
Rf Front End ◽  
Quadrature Signals

In this paper, A Software-Defined Radio (SDR) RF front-end is presented that contains merged LNA and mixers, VGAs, and frequency synthesizer, supporting various wireless communication standards in 0.1-2 GHz while guaranteeing a power/performance trade-off at any time. The proposed low power RF front-end uses the folded and current reuse techniques. for 0.18 um RF CMOS technology with 1.8V supply voltage. In the receive path the proposed design achieves a Noise Figure of 3.8 dB at 160 MHz and 5.5 dB at 2GHz. The Output-referred 3rd-order Intercept Point (OIP3) is high up to 21.3 dBm at 800 MHz. The voltage gain of the front- end is between 16-44 dB. The phase mismatch of LO quadrature signals is lower than 3deg.It consumes 13.8 mW at the 1.7V supply.

scholarly journals A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

2011 ◽  
Vol 2011 ◽  
pp. 1-10 ◽  
Author(s):  
Indranil Hatai ◽  
Indrajit Chakrabarti
Keyword(s):  
Software Defined Radio ◽  
High Speed ◽  
High Performance ◽  
Frequency Synthesizer ◽  
Dynamic Range ◽  
Fpga Implementation ◽  
Clock Frequency ◽  
System Clock ◽  
Quarter Wave ◽  
The Individual

This paper deals with an FPGA implementation of a high performance FM modulator and demodulator for software defined radio (SDR) system. The individual component of proposed FM modulator and demodulator has been optimized in such a way that the overall design consists of a high-speed, area optimized and low-power features. The modulator and demodulator contain an optimized direct digital frequency synthesizer (DDFS) based on quarter-wave symmetry technique for generating the carrier frequency with spurious free dynamic range (SFDR) of more than 64 dB. The FM modulator uses pipelined version of the DDFS to support the up conversion in the digital domain. The proposed FM modulator and demodulator has been implemented and tested using XC2VP30-7ff896 FPGA as a target device and can operate at a maximum frequency of 334.5 MHz and 131 MHz involving around 1.93 K and 6.4 K equivalent gates for FM modulator and FM demodulator respectively. After applying a 10 KHz triangular wave input and by setting the system clock frequency to 100 MHz using Xpower the power has been calculated. The FM modulator consumes 107.67 mW power while FM demodulator consumes 108.67 mW power for the same input running at same data rate.

scholarly journals A Quadrature Single Side-Band Mixer with Passive Negative Resistance in Software-Defined Frequency Synthesizer

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3455 ◽  
Author(s):  
Dongsheng Liu ◽  
Ang Hu ◽  
Kefeng Zhang
Keyword(s):  
Software Defined Radio ◽  
Frequency Synthesizer ◽  
Field Effect Transistors ◽  
Negative Resistance ◽  
Frequency Synthesizers ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Side Band ◽  
Single Side ◽  
Single Side Band

Software-defined radio (SDR) is a good solution for complying with the existing and incoming protocols for emerging wireless sensor networks (WSN) and internet of things (IoT) applications. The frequency synthesizer in a SDR tranceiver usually consists of a phase locked loop (PLL) and a post synthesizer. The PLL is the narrow band signal source and the post synthesizer generates wideband outputs by mixing and dividing. Compared with a frequency synthesizer utilizing the wideband PLL, this synthesizer features relatively constant loop parameters and mitigates the requirement for the oscillator. In this paper, a quadrature single side-band (QSSB) mixer with the proposed passive negative resistance (PNR) for frequency mixing in a post synthesizer is presented. The PNR is achieved by biasing the Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET) of the cross-coupled pair at the deep-triode region periodically and incorporates an inductor and a cap-array as the mixer load. Compared with the traditional single side-band mixers utilizing Inductor-Capacitor (LC) resonant loads or quality factor enhanced (Q-enhanced) LC resonant loads, which suffer from a selectivity versus working range trade-off, the mixer employing the proposed loading structure provides not only a wide operating range, but also a superior image side-band rejection ratio (ISRR). Moreover, the oscillating risk in conventional mixers adopting Q-enhanced LC resonant loads is eliminated. A wideband frequency synthesizer employing the proposed mixer was implemented in a TSMC 0.18 µm CMOS process and the mixer performed ISRR of 40–57 dB and 30–57 dB across 2.5–3 GHz and 2.3–3.2 GHz, respectively. The power consumption of the QSSB mixer, including buffer, is 18 mA from a 1.8 V supply and the active area is 0.445 mm2. The measurement results provide validation that the proposed QSSB mixer is suitable for wideband software-defined frequency synthesizers and other frequency generating systems.

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