The design of low power memory cells is the dream of engineers in memory design. A Darlington-based 8T CNTFET SRAM cell is suggested in this paper. It is called the proposed P_CNTFET Darlington 8T SRAM Cell. Compared with that of the traditional 6T and 8T CNTFET SRAM cells, the power and noise performances of the proposed SRAM cell are comparable. Compared to the traditional SRAM cells, the write, hold, read and dynamic power consumption of the proposed cell is much lower. The CNTFET parameters are optimized to boost the noise margin performance of the suggested bit cell. For optimized parameters, the power consumption and SNM of the proposed cell are compared with conventional cells. In contrast to the conventional cells, the HSNM and WSNM of the proposed cell are improved by 6.25% and 66.6%. The proposed cell’s RSNM is 38% greater than the traditional 6T SRAM cell. The proposed cell’s RSNM is 3.33% less than the traditional 8T SRAM cell. MOSFET is also used to implement the proposed SRAM cell and its noise margin and power performance are compared with traditional MOSFET-based SRAM cells. As with the conventional cells, the MOSFET-based implementation of the proposed cell power and SNM performance is also very good. The simulation is done with the HSPICE simulation tool using the Stanford University 32[Formula: see text]nm CNTFET model.
Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors
