An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits

2016 ◽  
Vol 65 (2) ◽  
pp. 382-395 ◽  
Author(s):  
Lawrence T. Clark ◽  
Dan W. Patterson ◽  
Chandarasekaran Ramamurthy ◽  
Keith E. Holbert
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.


2016 ◽  
Vol 18 (1) ◽  
pp. 76-86
Author(s):  
N.N. Prokopenko ◽  
N.V. Butyrlagin ◽  
A.V. Bugakova ◽  
A.A. Ignashin

2020 ◽  
Vol 96 (3s) ◽  
pp. 169-174
Author(s):  
Ю.М. Герасимов ◽  
Н.Г. Григорьев ◽  
А.В. Кобыляцкий ◽  
Я.Я. Петричкович

Рассматриваются архитектурные, схемотехнические и конструктивно-топологические особенности асинхронного радиационно стойкого ОЗУ 1657РУ2У емкостью 16 Мбит с организацией (1Мx16)/(2Mx8), изготавливаемого по коммерческой КМОП-технологии объемного кремния уровня 130 нм. СБИС ОЗУ нечувствительна к эффекту «защелкивания», имеет повышенные дозовую стойкость и сбоеустойчивость при воздействии отдельных ядерных частиц (ОЯЧ), протонов и нейтронов (ТЧ). The paper highlights architectural, schematic and topological features of the radiation hardened 16 Mbit CMOS SRAM with configurable organization 1Mx16/2Mx8, which is immune to latch-up and with improved total dose and heavy particles tolerance.


2019 ◽  
Vol 18 ◽  
pp. 1089-1096 ◽  
Author(s):  
Abdolah Amirany ◽  
Fahimeh Marvi ◽  
Kian Jafari ◽  
Ramin Rajaei
Keyword(s):  

Author(s):  
Ebrahim M. Al Seragi ◽  
Subhra Dash ◽  
K. Muthuseenu ◽  
John D. Cressler ◽  
Hugh J. Barnaby ◽  
...  

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1572
Author(s):  
Ehab A. Hamed ◽  
Inhee Lee

In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design.


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