RMSS: an efficient recovery management scheme on NAND flash memory based solid state disk

NAND flash memory has been successfully employed in storage system due to its advantages such as performance, resistance, and capacity. NAND flash memory based solid state disk (SSD) has started to replace disk in numerous environments. However, the poor endurance offered by these SSDs continues to be their key shortcoming. To improve SSD endurance, we propose a static wear-leveling algorithm with variable threshold (WLVT). In contrast with traditional algorithm with fixed threshold, WLVT adjusts the value of threshold, so that each block can simultaneously reach the erasure times that the manufacturer gives when life of SSD is over. Therefore, available erasure time of each block will be fully utilized when SSD fails. Experimental results show that the endurance of the SSD is significantly improved.

Download Full-text

Lifetime-Aware Capacity Dynamic Adjusting for Solid State Disk

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.513-517.3630 ◽

2014 ◽

Vol 513-517 ◽

pp. 3630-3633

Author(s):

Kai Bu ◽

Hai Jun Liu ◽

Hui Xu ◽

Zhao Lin Sun

Keyword(s):

Solid State ◽

Flash Memory ◽

Nand Flash ◽

Nand Flash Memory ◽

Solid State Disk

In this paper, we analyzed the endurance of Nand Flash memory and then proposed a level adjusting scheme to use the MLC Flash dynamically to storage different amount of data levels through the entire lifetime. The result shows that the MLC SSD adopting this method could be totally written 4.8X more data than conventional MLC SSD and 16.5% more than SLC SSD.

Download Full-text

PCI Express-Based NVMe Solid State Disk

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.464.365 ◽

2013 ◽

Vol 464 ◽

pp. 365-368 ◽

Cited By ~ 3

Author(s):

Ji Jun Hung ◽

Kai Bu ◽

Zhao Lin Sun ◽

Jie Tao Diao ◽

Jian Bin Liu

Keyword(s):

Flash Memory ◽

Nand Flash ◽

Nand Flash Memory ◽

Detailed Design ◽

Pci Express ◽

Storage Media ◽

Solid State Disk ◽

Memory Card ◽

Non Volatile Memory ◽

Flash Translation Layer

This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.

Download Full-text

17x Reliability Enhanced LDPC Code with Burst-Error Masking and High-Precision LLR for Highly Reliable Solid-State-Drives with TLC NAND Flash Memory

2016 IEEE 8th International Memory Workshop (IMW) ◽

10.1109/imw.2016.7493561 ◽

2016 ◽

Cited By ~ 1

Author(s):

Tsukasa Tokutomi ◽

Ken Takeuchi

Keyword(s):

Solid State ◽

High Precision ◽

Flash Memory ◽

Ldpc Code ◽

Nand Flash ◽

Solid State Drives ◽

Nand Flash Memory ◽

Burst Error ◽

Error Masking

Download Full-text

A Novel Bit-Flipping LDPC Decoder for Solid-State Data Storage

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.513-517.2094 ◽

2014 ◽

Vol 513-517 ◽

pp. 2094-2098 ◽

Cited By ~ 1

Author(s):

Wen Zhe Zhao ◽

Kai Zhao ◽

Qiu Bo Chen ◽

Min Jie Lv ◽

Zuo Xun Hou

Keyword(s):

Solid State ◽

Error Correction ◽

Data Storage ◽

Flash Memory ◽

Message Passing ◽

High Speed ◽

Design Solution ◽

Nand Flash ◽

Nand Flash Memory ◽

State Data

This paper concerns the design of high-speed and low-cost LDPC code bit-flipping decoder. Due to its inferior error correction strength, bit-flipping decoding received very little attention compared with message-passing decoding. Nevertheless, emerging flash-based solid-state data storage systems inherently favor a hybrid bit-flipping/message-passing decoding strategy, due to the significant dynamics and variation of NAND flash memory raw storage reliability. Therefore, for the first time highly efficient silicon implementation of bit-flipping decoder becomes a practically relevant topic. To address the drawbacks caused by the global search operation in conventional bit-flipping decoding, this paper presents a novel bit-flipping decoder design. Decoding simulations and ASIC design show that the proposed design solution can achieve upto 80% higher decoding throughput and meanwhile consume upto 50% less silicon cost, while maintaining almost the same decoding error correction strength.

Download Full-text