A 77-dB Dynamic Range Low-Power Variable-Gain Transimpedance Amplifier for Linear LADAR

2018 ◽  
Vol 65 (2) ◽  
pp. 171-175 ◽  
Author(s):  
Rui Ma ◽  
Maliang Liu ◽  
Hao Zheng ◽  
Zhangming Zhu
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Transimpedance Amplifier ◽  
Variable Gain

Low-power digitally-controlled variable gain attenuator and LNA with high gain dynamic range for sub-GHz ISM bands

2012 ◽  
Vol 73 (1) ◽  
pp. 169-183
Author(s):  
Mathieu Périn ◽  
Sébastien Darfeuille ◽  
Olivier Aymard ◽  
Patrice Gamand ◽  
Corinne Berland
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
High Gain ◽  
Variable Gain ◽  
Digitally Controlled

scholarly journals A 4 GHz Single-to-Differential Cross-Coupled Variable-Gain Transimpedance Amplifier for Optical Communication

Electronics ◽  
2021 ◽  
Vol 10 (23) ◽  
pp. 3042
Author(s):  
Samuel B. S. Lee ◽  
Kiat Seng Yeo
Keyword(s):  
Optical Communication ◽  
Dynamic Range ◽  
Visible Light Communication ◽  
Cmos Process ◽  
Transimpedance Amplifier ◽  
Bandwidth Enhancement ◽  
Variable Gain ◽  
Noise Current ◽  
Dc Power ◽  
Capacitive Load

This letter presents an inductorless transimpedance amplifier (TIA) for visible light communication, using the UMC 40 nm CMOS process. It consists of a single-to-differential input stage with a modified cross-coupled regulated cascode design, followed by a modified fT-doubler mid-stage with a combined active inductor and capacitive degeneration design for bandwidth-enhancement and differential output. The mid-stage also has an attached common-mode feedback (CMFB) circuit. Both the input and mid-stages have gain-varying and peaking-varying functions. It has a measured gain range of 37.5–58.7 dBΩ and 4.15 GHz bandwidth using a 0.5 pF capacitive load. The gain range results in an input dynamic range of 33.2 µA–1.46 mA. Its input referred noise current is 10.7 pA/Hz, core DC power consumption is 7.84 mW from a VDDTIA of 1.6 V and core area is 39 µm × 26 µm.

A Low-Noise, Low-Power, Wide Dynamic Range Logarithmic Amplifier for Biomedical Applications

2018 ◽  
Vol 27 (07) ◽  
pp. 1850104 ◽  
Author(s):  
Yuwadee Sundarasaradula ◽  
Apinunt Thanachayanont
Keyword(s):  
Low Power ◽  
Biomedical Applications ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Low Noise ◽  
Power Supply Voltage ◽  
Wide Dynamic Range ◽  
Dc Offset ◽  
Limiting Amplifier ◽  
Logarithmic Amplifier

This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18[Formula: see text][Formula: see text]m CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027[Formula: see text]mm2. The overall circuit consumes 9.75[Formula: see text][Formula: see text]W from a single 1.5[Formula: see text]V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80[Formula: see text]dB input dynamic range (from 10[Formula: see text][Formula: see text]V to 100[Formula: see text]mV), a bandwidth of 4[Formula: see text]Hz–10[Formula: see text]kHz, and a total input-referred noise of 5.52[Formula: see text][Formula: see text]V.

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