scholarly journals A 4 GHz Single-to-Differential Cross-Coupled Variable-Gain Transimpedance Amplifier for Optical Communication

Electronics ◽  
2021 ◽  
Vol 10 (23) ◽  
pp. 3042
Author(s):  
Samuel B. S. Lee ◽  
Kiat Seng Yeo
Keyword(s):  
Optical Communication ◽  
Dynamic Range ◽  
Visible Light Communication ◽  
Cmos Process ◽  
Transimpedance Amplifier ◽  
Bandwidth Enhancement ◽  
Variable Gain ◽  
Noise Current ◽  
Dc Power ◽  
Capacitive Load

This letter presents an inductorless transimpedance amplifier (TIA) for visible light communication, using the UMC 40 nm CMOS process. It consists of a single-to-differential input stage with a modified cross-coupled regulated cascode design, followed by a modified fT-doubler mid-stage with a combined active inductor and capacitive degeneration design for bandwidth-enhancement and differential output. The mid-stage also has an attached common-mode feedback (CMFB) circuit. Both the input and mid-stages have gain-varying and peaking-varying functions. It has a measured gain range of 37.5–58.7 dBΩ and 4.15 GHz bandwidth using a 0.5 pF capacitive load. The gain range results in an input dynamic range of 33.2 µA–1.46 mA. Its input referred noise current is 10.7 pA/Hz, core DC power consumption is 7.84 mW from a VDDTIA of 1.6 V and core area is 39 µm × 26 µm.

scholarly journals Design of Differential Variable-Gain Transimpedance Amplifier in 0.18 µm SiGe BiCMOS

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1058
Author(s):  
Samuel B.S. Lee ◽  
Hang Liu ◽  
Kiat Seng Yeo ◽  
Jer-Ming Chen ◽  
Xiaopeng Yu
Keyword(s):  
Dynamic Range ◽  
Third Order ◽  
Transimpedance Amplifiers ◽  
Variable Gain ◽  
Gain Variation ◽  
Bicmos Technology ◽  
Capacitive Load ◽  
Sige Bicmos ◽  
Amplifier Stage ◽  
On Chip

This paper presents two new inductorless differential variable-gain transimpedance amplifiers (DVGTIA) with voltage bias controlled variable gain designed in TowerJazz’s 0.18 µm SiGe BiCMOS technology (using CMOS transistors only). Both consist of a modified differential cross-coupled regulated cascode preamplifier stage and a cascaded amplifier stage with bias-controlled gain-variation and third-order interleaving feedback. The designs have wide measured transimpedance gain ranges of 24.5–60.6 dBΩ and 27.8–62.8 dBΩ with bandwidth above 6.42 GHz and 5.22 GHz for DVGTIA designs 1 and 2 respectively. The core power consumptions are 30.7 mW and 27.5 mW from a 1.8 V supply and the input referred noise currents are 10.3 pA/√Hz and 21.7 pA/√Hz. The DVGTIA designs 1 and 2 have a dynamic range of 40.4 µA to 3 mA and 76.8 µA to 2.7 mA making both suitable for real photodetectors with an on-chip photodetector capacitive load of 250 fF. Both designs are compact with a core area of 100 µm × 85 µm.

A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications

2022 ◽  
Vol 43 (1) ◽  
pp. 012401
Author(s):  
Quan Pan ◽  
Xiongshi Luo
Keyword(s):  
Optical Measurement ◽  
Supply Voltage ◽  
Electrical Measurement ◽  
High Gain ◽  
Input Device ◽  
Cmos Process ◽  
Transimpedance Amplifier ◽  
Bandwidth Enhancement ◽  
Inductive Peaking ◽  
Capacitive Loading

Abstract This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process. Multiple bandwidth enhancement techniques, including input bonding wire, input series on-chip inductive peaking and negative capacitance compensation, are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device, achieving an overall bandwidth enhancement ratio of 8.5. The electrical measurement shows TIA achieves 58 dBΩ up to 12.7 GHz with a 180-fF off-chip photodetector. The optical measurement demonstrates a clear open eye of 20 Gb/s. The TIA dissipates 4 mW from a 1.2-V supply voltage.

scholarly journals A 79 dBΩ 1.2 GHz Low-Noise Single-Ended CMOS Transimpedance Amplifier for High-Performance OTDR Applications

2019 ◽  
Vol 15 (2) ◽  
pp. 113-118
Author(s):  
Agata Romanova ◽  
Vaidotas Barzdenas
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Low Noise ◽  
Cmos Process ◽  
Transimpedance Amplifier ◽  
Output Buffer ◽  
Noise Current ◽  
Resistive Feedback ◽  
Optical Time ◽  
And Performance

AbstractThe work reports on the design and performance of a low-noise low-cost CMOS transimpedance amplifier (TIA). The proposed circuit shall be employed in optical time-domain reflectometers and is implemented using an affordable 0.18 µm 1.8 V CMOS process. The approach preserves the benefits of a classical feedback structure while addressing the noise problem of conventional feed-forward and resistive feedback architectures via the usage of noise-efficient capacitive feedback. Circuit-level modifications are proposed to mitigate the voltage headroom and DC current issues. The suggested design achieves a total gain of 82 dBΩ (79 dBΩ after the output buffer) within the bandwidth of 1.2 GHz while operating with a total input capacitance of 0.7 pF. The simulated average input-referred noise current density is below 1.8 pA/sqrt(Hz) with the power consumption of the complete amplifier including the output buffer being 21 mW.

scholarly journals A Capacitive Feedback Transimpedance Amplifier with a DC Feedback Loop Using a Transistor for High DC Dynamic Range

Sensors ◽  
2020 ◽  
Vol 20 (17) ◽  
pp. 4716
Author(s):  
Jung-hoon Noh
Keyword(s):  
Feedback Loop ◽  
Thermal Noise ◽  
Dynamic Range ◽  
System Stability ◽  
Design Parameters ◽  
Transimpedance Amplifier ◽  
Simple Method ◽  
Noise Current ◽  
Dc Component ◽  
Capacitive Feedback

This study proposes a capacitive feedback transimpedance amplifier (CF-TIA) using a transistor in the direct current (DC) feedback loop for high DC dynamic range. In some applications, the background DC input can vary widely from the minimum to the maximum, and TIA have to sense the target signal even on the top of the maximum DC input. In a conventional CF-TIA, however, the allowable DC input is constrained by the value of the resistor in the DC feedback loop. To allow a fairly high DC input, the resistor is set to a very low value. This causes the thermal noise current to increase significantly. The increased thermal noise is always present even in the minimum DC input, thus degrading the overall noise performance. The circuit proposed herein overcomes this shortcoming by using the transistor instead of the resistor. The adverse effect of the parasitic capacitance of the transistor on system stability is compensated for as well. Then, the analyses of the overall frequency response and design parameters, including the cut-off frequency and attenuation ratio associated with system stability, are presented for the proposed circuit. In addition, in order to cope with the problem that stability is dependent on the amount of DC input, a simple method for ensuring system stability regardless of DC component value is introduced. The presented analyses and the method are generalized for all CF-TIA applications.

scholarly journals Ultra compact multi-standard low-noise amplifiers in 28 nm CMOS with inductive peaking

2017 ◽  
Vol 10 (1) ◽  
pp. 47-57
Author(s):  
Elena Sobotta ◽  
Guido Belfiore ◽  
Frank Ellinger
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Cmos Process ◽  
Bandwidth Enhancement ◽  
Dc Power ◽  
Active Inductors ◽  
Inductive Peaking ◽  
Noise Amplifier ◽  
28 Nm

This work presents the design of two compact multi-standard low-noise amplifier (LNA) in a 28 nm low-power bulk CMOS process. The transistor parameters were optimized by the gm/ID method taking into account the parasitics and the behavior of highly scaled transistors. To cover the industrial science medical (ISM)-bands around 2.4 and 5.8 GHz, the WLAN band as well as the Ku band a bandwidth enhancement is required. Two versions of LNAs, one with vertical inductors and one with active inductors, are implemented and verified by measurements. The noise figure (NF) exhibits 4.2 dB for the LNA with active inductors and 3.5 dB for the LNA with vertical inductors. The voltage gain reaches 12.8 and 13.4 dB, respectively, with a 3 dB-bandwidth of 20 GHz. Both input referred 1-dB-compression points are higher than −12 dBm making the chips attractive for communication standards with high linearity requirements. The chips consume 53 mW DC power and the LNA with active inductors occupies a core area of only 0.0018 mm2, whereas the version with vertical inductors requires 0.021 mm2.

A 40Gb/s Transimpedance Amplifier Using Modified Regulated Cascode for Optical Fiber Communication

2012 ◽  
Vol 236-237 ◽  
pp. 958-963
Author(s):  
Ying Mei Chen ◽  
Tao Wang ◽  
Jin Fei Wang ◽  
Jian Wei Gong ◽  
Lei Zhu
Keyword(s):  
Optical Fiber ◽  
Optical Fiber Communication ◽  
Cmos Technology ◽  
Transimpedance Amplifier ◽  
Fiber Communication ◽  
Noise Current ◽  
Input Noise ◽  
Dc Power ◽  
Active Feedback ◽  
Equivalent Input Noise

This paper describes the design of a 40 Gb/s transimpedance amplifier (TIA) for high-density optical fiber communication system. This TIA incorporates modified regulated cascode (RGC), three order intersecting active feedback and passive feedback. Consuming a DC power of 14.5 mW, the single-ended circuit provides a transimpedance gain of 49.5 dB and a -3dB bandwidth up to 40 GHz in IBM 90-nm CMOS technology with a 1.2 V supply. Simulation results show the equivalent input noise current integrated from 1 MHz to 30 GHz is about 6.6 Arms

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