64 dB Dynamic-Range 810 μW 90 MHz Fully-Differential Flipped-Source-Follower Analog Filter in 28nm-CMOS

Author(s):  
Marcello De Matteis ◽  
Nicolas Galante ◽  
Federico Fary ◽  
Elia Vallicelli ◽  
Andrea Baschirotto
2021 ◽  
Vol 11 (2) ◽  
pp. 15
Author(s):  
Marcello De Matteis ◽  
Federico Fary ◽  
Elia A. Vallicelli ◽  
Andrea Baschirotto

This paper presents a fourth-order continuous-time analog filter based on the cascade of two flipped-source-follower (FSF) biquadratic (biquad) cells. The FSF biquad adopts two interacting loops (the first due to the classic source-follower, and the second to the additional gain path) which lower the impedances of all circuit nodes with relevant benefits in terms of noise power reduction and linearity enhancement. The presented device was integrated in 28 nm CMOS and featured 100 MHz −3 dB bandwidth with 67 dB Dynamic-Range. Input IP3 was 12 dBm at 10 and 11 MHz input tone frequencies. Total power consumption was 0.968 mW (0.484 mW per cell). Hence, the filter performed one of the highest figures-of-merit (160.7 dBJ-1) compared with analog state-of-the-art filters.


Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 563
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Pasquale Tommasino ◽  
Alessandro Trifiletti

Multi-GHz lowpass filters are key components for many RF applications and are required for the implementation of integrated high-speed analog-to-digital and digital-to-analog converters and optical communication systems. In the last two decades, integrated filters in the Multi-GHz range have been implemented using III-V or SiGe technologies. In all cases in which the size of passive components is a concern, inductorless designs are preferred. Furthermore, due to the recent development of high-speed and high-resolution data converters, highly linear multi-GHz filters are required more and more. Classical open loop topologies are not able to achieve high linearity, and closed loop filters are preferred in all applications where linearity is a key requirement. In this work, we present a fully differential BiCMOS implementation of the classical Sallen Key filter, which is able to operate up to about 10 GHz by exploiting both the bipolar and MOS transistors of a commercial 55-nm BiCMOS technology. The layout of the biquad filter has been implemented, and the results of post-layout simulations are reported. The biquad stage exhibits excellent SFDR (64 dB) and dynamic range (about 50 dB) due to the closed loop operation, and good power efficiency (0.94 pW/Hz/pole) with respect to comparable active inductorless lowpass filters reported in the literature. Moreover, unlike other filters, it exploits the different active devices offered by commercial SiGe BiCMOS technologies. Parametric and Monte Carlo simulations are also included to assess the robustness of the proposed biquad filter against PVT and mismatch variations.


2007 ◽  
Vol 51 (3) ◽  
pp. 181-189 ◽  
Author(s):  
Bilgin Metin ◽  
Shahram Minaei ◽  
Oguzhan Cicekoglu
Keyword(s):  

2021 ◽  
Author(s):  
Bendong Sun

This thesis deals with the design of a low-voltage fully-differential CMOS current-mode preamplifier for optical communications. An in-depth comparative analysis of the building blocks of low-voltage CMOS current-mode circuits is carried out. Two new bandwidth enhancement techniques, namely inductor series-peaking and current feedback, are introduced and implemented in the design. The feedback also reduces the value of the series-peaking inductor. The minimum supply voltage of the amplifier is only one threshold voltage plus one pinch-off voltage. The preamplifier has a balanced differential topology such that the effect of bias dependent mismatches is minimized and the amplifier is insensitive to the switching noise caused by the digital circuitry. Negative differential current feedbacks are implemented to boost the bandwidth and increase the dynamic range.


2015 ◽  
Vol 25 (03) ◽  
pp. 1640019 ◽  
Author(s):  
Daniel Arbet ◽  
Gabriel Nagy ◽  
Martin Kováč ◽  
Viera Stopjaková

In this paper, a fully differential difference amplifier (FDDA) designed in 0.35[Formula: see text][Formula: see text]m CMOS technology is presented. The proposed amplifier reaches high dynamic range (DR) and low input referred noise. Comparison of noise performance of the proposed FDDA to an ordinary differential amplifier has been performed. Achieved results prove that the developed amplifier circuit can be advantageously used in applications that require a fully differential signal. Then, simulation results have been verified by the measurement of prototyped chips. In our work, the proposed amplifier was experimentally employed in the analog frontend of the readout interface (RI) for a Micro-Electro-Mechanical-Systems (MEMS) capacitive microphone.


2014 ◽  
Vol 23 (09) ◽  
pp. 1450124 ◽  
Author(s):  
SOHEYL ZIABAKHSH ◽  
HOSEIN ALAVI-RAD ◽  
MORTEZA ALINIA AHANDANI ◽  
MUSTAPHA C. E. YAGOUB

In this paper, we optimized the performance of a 2.4 GHz variable gain low-noise amplifier for WLAN applications which provides high dynamic range with relatively low power consumption. First, the differential evolution algorithm was used to optimize the width of input transistors, then the tunable on-chip switching stage method was applied to control the amplifier gain when the input signal increases. The optimization was performed in terms of gain, noise figure (NF), IIP3 and power dissipation. The LNA has achieved a variable gain from 16.55 to 20.45 dB with excellent NF between 1.63 and 1.74 dB. Furthermore, the proposed circuit achieves a third order input intercept point of 6.6 dBm. It consumes only 10 mW from a 1.5 V supply.


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