scholarly journals A 28 nm CMOS 100 MHz 67 dB-Dynamic-Range 968 µW Flipped-Source-Follower Analog Filter

2021 ◽  
Vol 11 (2) ◽  
pp. 15
Author(s):  
Marcello De Matteis ◽  
Federico Fary ◽  
Elia A. Vallicelli ◽  
Andrea Baschirotto
Keyword(s):  
Dynamic Range ◽  
Power Reduction ◽  
Total Power ◽  
Noise Power ◽  
Analog Filter ◽  
Figures Of Merit ◽  
Total Power Consumption ◽  
Source Follower ◽  
Order Continuous ◽  
28 Nm

This paper presents a fourth-order continuous-time analog filter based on the cascade of two flipped-source-follower (FSF) biquadratic (biquad) cells. The FSF biquad adopts two interacting loops (the first due to the classic source-follower, and the second to the additional gain path) which lower the impedances of all circuit nodes with relevant benefits in terms of noise power reduction and linearity enhancement. The presented device was integrated in 28 nm CMOS and featured 100 MHz −3 dB bandwidth with 67 dB Dynamic-Range. Input IP3 was 12 dBm at 10 and 11 MHz input tone frequencies. Total power consumption was 0.968 mW (0.484 mW per cell). Hence, the filter performed one of the highest figures-of-merit (160.7 dBJ-1) compared with analog state-of-the-art filters.

A CMOS Image Sensor with a Novel Passive Pixel Array and High Precision Current Amplifier for a Compact Digital X-ray Detector

2020 ◽  
Vol 10 (11) ◽  
pp. 2745-2753
Author(s):  
Jimin Cheon ◽  
Dongmyung Lee ◽  
Hojong Choi
Keyword(s):  
High Precision ◽  
Dynamic Range ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Total Power ◽  
Cmos Process ◽  
Current Amplifier ◽  
X Ray ◽  
Total Power Consumption ◽  
Pixel Array

An active pixel sensor (APS) in a digital X-ray detector is the dominant circuitry for a CMOS image sensor (CIS) despite its lower fill factor (FF) compared to that of a passive pixel sensor (PPS). Although the PPS provides higher FF, its overall signal-to-noise ratio (SNR) is lower than that of the APS. The required high resolution and small focal plane can be achieved by reducing the number of transistors and contacts per pixel. We proposed a novel passive pixel array and a high precision current amplifier to improve the dynamic range (DR) without minimizing the sensitivity for diagnostic compact digital X-ray detector applications. The PPS can be an alternative to improve the FF. However, size reduction of the feedback capacitor causes degradation of SNR performance. This paper proposes a novel PPS based on readout and amplification circuits with a high precision current amplifier to minimize performance degradation. The expected result was attained with a 0.35-μm CMOS process parameter with power supply voltage of 3.3 V. The proposed PPS has a saturation signal of 1.5 V, dynamic range of 63.5 dB, and total power consumption of 13.47 mW. Therefore, the proposed PPS readout circuit improves the dynamic range without sacrificing the sensitivity.

Power Reduction Techniques in Cloud Data Centers

2014 ◽  
Vol 1061-1062 ◽  
pp. 1070-1073
Author(s):  
Lei Tang ◽  
Zheng Ce Cai ◽  
Guo Long Chen ◽  
Xian Wei Li
Keyword(s):  
Cloud Computing ◽  
Data Centers ◽  
Large Fraction ◽  
Power Reduction ◽  
Cloud Services ◽  
Total Power ◽  
Cloud Data ◽  
Reduction Techniques ◽  
Total Power Consumption ◽  
Cloud Data Centers

In recent years, cloud computing has received much attention from both academia and engineering areas. With more and more companies beginning to provide cloud services, more and more data centers are being built. Recent studies show that the energy consumed by cloud data centers accounts for a large fraction of the total power consumption today. This motivates us to survey power reduction techniques in cloud data centers.

Design Methodology for Multipliers with Active Leakage and Dynamic Power Reduction

2012 ◽  
Vol 182-183 ◽  
pp. 1440-1445
Author(s):  
Xi Tian ◽  
Fei Qiao ◽  
Zai Wang Dong ◽  
Yu Jun Liu ◽  
Yu Ting Zhao
Keyword(s):  
Input Signal ◽  
Power Dissipation ◽  
Design Methodology ◽  
Dynamic Range ◽  
Power Reduction ◽  
Total Power ◽  
Power Gating ◽  
Dynamic Power ◽  
On Chip ◽  
Novel Design

A novel design methodology for multipliers to reducing both active leakage and dynamic power using dynamic power gating is presented, where sleep transistors are inserted between the real and virtual ground rails of various parts of the multiplier which could be selectively turned on/off. On-chip sleep signals are generated from one input signal of the multiplier which has larger dynamic range. By detecting the magnitude of the input signal, the idle parts of the multiplier are identified and the power gating schemes are dynamically applied even when the multiplier is performing useful computation. Simulations show that the total power dissipation of the proposed multiplier could be reduced up to 39.3% in a typical DSP application.

scholarly journals Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

2018 ◽  
Vol 8 (6) ◽  
pp. 4922
Author(s):  
Anil Khatak ◽  
Manoj Kumar ◽  
Sanjeev Dhull
Keyword(s):  
Power Consumption ◽  
Leakage Current ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Power Reduction ◽  
Total Power ◽  
Low Power Consumption ◽  
Power Gating ◽  
Reduction Techniques ◽  
Total Power Consumption

To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

A three-quarter watt seismic station

1972 ◽  
Vol 62 (4) ◽  
pp. 985-990 ◽  
Author(s):  
K. J. Muirhead ◽  
D. W. Simpson
Keyword(s):  
Dynamic Range ◽  
Seismic Station ◽  
Low Cost ◽  
Seismic Signal ◽  
Total Power ◽  
Time Signal ◽  
Direct Recording ◽  
Total Power Consumption ◽  
Seismic Recording ◽  
Crystal Clock

Abstract A low-power, low-cost instrument using slow speed, direct recording on magnetic tape provides continuous unattended seismic recording in excess of 1 month. The seismic signal is recorded at two gain levels separated by 26 db with a total dynamic range of greater than 70 db. A high-accuracy crystal clock with fully coded digital output and a crystal stabilized radio for reference time-signal reception provide timing to better than 0.1 sec throughout the recording period. Total power consumption is less than 34 watts which enables operation for 1 month on dry cell batteries. The weight of the complete system including seismometer and batteries is less than 100 lb. Ten instruments have been used to record seismic signals ranging from localized microearthquake activity to explosions and teleseismic events.

Design of Low Power and High Precision Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) Based on Piecewise Capacitance and Calibration Technique

2020 ◽  
Vol 15 (4) ◽  
pp. 478-486
Author(s):  
Sheng-Biao An ◽  
Li-Xin Zhao ◽  
Shi-Cong Yang ◽  
Tao An ◽  
Rui-Xia Yang
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Dynamic Range ◽  
Sar Adc ◽  
Total Power ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Total Power Consumption

This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%. The test chip fabricated in 180 nm Complementary Metal Oxide Semiconductor (CMOS) occupied an active area of 0.12 mm 2 . At 10 MS/s, a signal-to-noise and distortion ratio (SNDR) of 57.70 dB and a spurious-free dynamic range (SFDR) of 55.63 dB are measured with 1.68 Vpp differential-mode input signal. The total power consumption is 690 μW corresponding to 67 fJ/conversion step figure of merit.

Design of a 10-Bit High Performance Current-Steering DAC with a Novel Nested Decoder Based on Domino Logic

2015 ◽  
Vol 24 (06) ◽  
pp. 1550086 ◽  
Author(s):  
Masoud Nazari ◽  
Leila Sharifi ◽  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Range ◽  
Logic Gates ◽  
Cmos Technology ◽  
Total Power ◽  
Current Steering ◽  
Domino Logic ◽  
Chip Area ◽  
Total Power Consumption

In this paper, a 10-bit 8-2 segmented current-steering digital-to-analog converter (DAC) is presented which uses a novel nested binary to thermometer (BT) decoder based on domino logic gates. High accuracy and high performances are achieved with this structure. The proposed decoder has a pipelining scheme and it is designed symmetrically in three stages with repeatable logic gates. Thus, power consumption, chip area and the number of control signals are reduced. The proposed DAC is simulated in 0.18-μm CMOS technology and the spurious-free dynamic range (SFDR) is 65.3 dB over a 500 MHz output bandwidth at 1 GS/s. Total power consumption of the designed DAC is only 23.4 mW while the digital and analog supply voltages are 1.2 and 1.8 V, respectively. The active area of the proposed DAC is equal to 0.3 mm2.

A 12-bit 1-MS/s 26-μW SAR ADC for Sensor Applications

2018 ◽  
Vol 3 (1) ◽  
Author(s):  
Yung-Hui Chung ◽  
Chia-Wei Yen ◽  
Cheng-Hsun Tsai
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Total Power ◽  
Measured Signal ◽  
Input Frequency ◽  
Dynamic Comparator ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Sensor Applications ◽  
Total Power Consumption

AbstractThis chapter presents an energy-efficient 12-bit 1-MS/s successive approximation register analog-to-digital converter (ADC) for sensor applications. A programmable dynamic comparator is proposed to suppress static current and maintain good linearity. A hybrid charge redistribution digital-to-analog converter is proposed to decrease the total capacitance, which would reduce the power consumption of the input and reference buffers. In the proposed ADC, its total input capacitance is only 700 fF, which greatly reduces the total power consumption of the analog frontend circuits. The 12-bit ADC is fabricated using 0.18-μm complementary metal-oxidesemiconductor technology, and it consumes only 26 μW from a 1 V supply at 1-MS/s. The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 60.1 and 72.6 dB, respectively. The measured effective number of bits (ENOB) for a 100 kHz input frequency is 9.7 bits. At the Nyquist input frequency, the measured SNDR and SFDR are 59.7 and 71 dB, respectively. The ENOB is maintained at 9.6 bits and the figure-of-merit is 33.5 fJ/conversion-step.

A 12-Bit 500-MS/s Current Steering CMOS DAC for High-Speed PLC Modems

2016 ◽  
Vol 25 (10) ◽  
pp. 1650122 ◽  
Author(s):  
Chan-Keun Kwon ◽  
Junil Moon ◽  
Soo-Won Kim
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Design Procedure ◽  
Weighted Averaging ◽  
Total Power ◽  
Cmos Process ◽  
Current Steering ◽  
Current Cell ◽  
Total Power Consumption

A 12-bit 500-MS/s current steering digital-to-analog converter (DAC) for high-speed power line communication (PLC) modems is presented in this paper. The performance of current steering DAC is limited by the current cell mismatches and glitch problems caused by switching timing errors. In this paper, the current cell design procedure is presented to minimize random mismatches. Then, a new data-weighted averaging (DWA) technique with fewer glitches and low hardware complexity is proposed to compensate for the gradient mismatch. Spurious-free dynamic range (SFDR) improvement and low complexity are effectively achieved by employing both a row–column structure and a (CSA) structure as the floor plan of the proposed DAC. The proposed DAC is implemented in a standard 0.18-[Formula: see text]m CMOS process with an active area of 2.445[Formula: see text]mm2, which achieves a differential non linearity (DNL) of 0.25[Formula: see text]LSB and an integral non-linearity (INL) of 0.19[Formula: see text]LSB. Additionally, the SFDR increases by 13.2[Formula: see text]dB (on average) when employing the proposed DWA technique. The total power consumption of the proposed DAC is 176[Formula: see text]mW from a 1.8-V supply voltage.

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