Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design

2017 ◽  
Vol 17 (1) ◽  
pp. 213-220 ◽  
Author(s):  
Ramin Rajaei ◽  
Sina Bakhtavari Mamaghani
2008 ◽  
Vol 44 (18) ◽  
pp. 1095 ◽  
Author(s):  
I. Hassoune ◽  
X. Yang ◽  
I. O'Connor ◽  
D. Navarro

2020 ◽  
Vol 29 (11) ◽  
pp. 2050176
Author(s):  
Feifei Deng ◽  
Guangjun Xie ◽  
Shaowei Wang ◽  
Xin Cheng ◽  
Yongqiang Zhang

Quantum-dot cellular automata (QCA) is a highly attractive alternative to CMOS for future digital circuit design, relying on its high-performance and low-power-consumption features. This paper analyzes and compares previously published five-input majority gates. These designs do not perform well in terms of physical properties, especially concerting power consumption. Therefore, an ultra-low-power five-input majority gate in one layer is proposed, which uses a minimum number of cells and smaller area, and achieves the expected highly polarized output compared with previous designs. In order to evaluate its practicability, a new one-bit coplanar full-adder is proposed. The analysis results show that this full-adder performs well compared with existing multilayer and single-layer designs. The number of cells of the proposed design is reduced by 7.14% to get the same area and clock delay compared with the best coplanar full-adder. In addition, its power dissipation is also reduced by 9.28% at 0.5[Formula: see text], 11.09% at 1[Formula: see text] and 12.66% at 1.5[Formula: see text] in terms of average energy dissipation compared with the best single-layer design. QCADesigner tool is used to verify the simulation results of the proposed designs and QCAPro tool is used to evaluate the power dissipation of all considered designs.


In the application of digital signal process multipliers play a vital role. With advances in technology, several researchers have tried and try to design multipliers which supply high speed, low power consumption, regularity of layout and thus less space or maybe combination of them in one multiplier factor. Thus, Compact VLSI design for four bit multiplier factor is planned during this paper that is appropriate for low power and high speed applications. Multiplier factor with high performance is achieved through the novel style of hybrid single bit full adder and Dadda algorithmic rule. The important path delay and power consumption of the planned multiplier factor square measure reduced by 65.9% and 24.5% severally when put next with existing multipliers. The planned multiplier factor is synthesized exploitation CADENCE five.1.0 EDA tool and simulated exploitation spectre virtuoso.


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