scholarly journals Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM

Micromachines ◽  
2020 ◽  
Vol 11 (11) ◽  
pp. 952
Author(s):  
Songyi Yoo ◽  
Wookyung Sun ◽  
Hyungsoon Shin
Keyword(s):  
Retention Time ◽  
Computer Aided Design ◽  
Memory Performance ◽  
Scaling Limit ◽  
Random Access ◽  
Random Access Memory ◽  
Memory Device ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Aided Design

A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory’s operating mechanism changes with the GB’s lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.

scholarly journals A Novel One-Transistor Dynamic Random-Access Memory (1T DRAM) Featuring Partially Inserted Wide-Bandgap Double Barriers for High-Temperature Applications

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 581 ◽  
Author(s):  
Myeongsun Kim ◽  
Jongmin Ha ◽  
Ikhyeon Kwon ◽  
Jae-Hee Han ◽  
Seongjae Cho ◽  
...  
Keyword(s):  
High Temperature ◽  
Computer Aided Design ◽  
Impact Ionization ◽  
Random Access ◽  
Random Access Memory ◽  
Memory Device ◽  
Wide Bandgap ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Wide Bandgap Semiconductor

These days, the demand on electronic systems operating at high temperature is increasing owing to bursting interest in applications adaptable to harsh environments on earth, as well as in the unpaved spaces in the universe. However, research on memory technologies suitable to high-temperature conditions have been seldom reported yet. In this work, a novel one-transistor dynamic random-access memory (1T DRAM) featuring the device channel with partially inserted wide-bandgap semiconductor material toward the high-temperature application is proposed and designed, and its device performances are investigated with an emphasis at 500 K. The possibilities of the program operation by impact ionization and the erase operation via drift conduction by a properly high drain voltage have been verified through a series of technology computer-aided design (TCAD) device simulations at 500 K. Analyses of the energy-band structures in the hold state reveals that the electrons stored in the channel can be effectively confined and retained by the surrounding thin wide-bandgap semiconductor barriers. Additionally, for more realistic and practical claims, transient characteristics of the proposed volatile memory device have been closely investigated quantifying the programming window and retention time. Although there is an inevitable degradation in state-1/state-0 current ratio compared with the case of room-temperature operation, the high-temperature operation capabilities of the proposed memory device at 500 K have been confirmed to fall into the regime permissible for practical use.

Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory

2021 ◽  
Vol 21 (8) ◽  
pp. 4216-4222
Author(s):  
Songyi Yoo ◽  
In-Man Kang ◽  
Sung-Jae Cho ◽  
Wookyung Sun ◽  
Hyungsoon Shin
Keyword(s):  
Strong Electric Field ◽  
Memory Performance ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Thin Body ◽  
Memory Cells ◽  
Access Memory ◽  
Memory Characteristics

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory’s data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, “0” state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.

A New Approach for Screening Retention Time Failure Bits in DRAM Device

2013 ◽  
Author(s):  
Bonggu Sung ◽  
Daejung Kim ◽  
Yongjik Park ◽  
Joo-Sun Choi
Keyword(s):  
Retention Time ◽  
Random Access ◽  
Random Access Memory ◽  
Cell Plate ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
New Approach ◽  
Root Cause ◽  
Storage Node ◽  
Node Voltage

Abstract In this paper, we investigate that Gate-Induced Drain Leakage (GIDL)-weak cells can be screened effectively by modulation of cell-plate voltage (VPlate) during retention time in dynamic random access memory (DRAM) with Negative Wordline bias scheme (NWL). Boosting storage-node voltage (VSP) by increase of VPlate is the root cause of generating additional GIDL fail bits.

scholarly journals Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1209
Author(s):  
Yejin Ha ◽  
Hyungsoon Shin ◽  
Wookyung Sun ◽  
Jisun Park
Keyword(s):  
Memory Performance ◽  
Random Access ◽  
Random Access Memory ◽  
Optimization Method ◽  
Memory Device ◽  
Circuit Optimization ◽  
Access Memory ◽  
Source Line ◽  
Bias Condition ◽  
Circuit Configuration

A capacitorless one-transistor dynamic random-access memory device (1T-DRAM) is proposed to resolve the scaling problem in conventional one-transistor one-capacitor random-access memory (1T-1C-DRAM). Most studies on 1T-DRAM focus on device-level operation to replace 1T-1C-DRAM. To utilize 1T-DRAM as a memory device, we must understand its circuit-level operation, in addition to its device-level operation. Therefore, we studied the memory performance depending on device location in an array circuit and the circuit configuration by using the 1T-DRAM structure reported in the literature. The simulation results show various disturbances and their effects on memory performance. These disturbances occurred because the voltages applied to each device during circuit operation are different. We analyzed the voltage that should be applied to each voltage line in the circuit to minimize device disturbance and determine the optimized bias condition and circuit structure to achieve a large sensing margin and realize operation as a memory device. The results indicate that the memory performance improves when the circuit has a source line and the bias conditions of the devices differ depending on the write data at the selected device cell. Therefore, the sensing margin of the 1T-DRAM used herein can expectedly be improved by applying the proposed source line (SL) structure.

Characterization of the Variable Retention Time in Dynamic Random Access Memory

2011 ◽  
Vol 58 (9) ◽  
pp. 2952-2958 ◽  
Author(s):  
Heesang Kim ◽  
Byoungchan Oh ◽  
Younghwan Son ◽  
Kyungdo Kim ◽  
Seon-Yong Cha ◽  
...  
Keyword(s):  
Retention Time ◽  
Random Access ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Variable Retention
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