Enhanced Linearity in CBRAM Synapse by Post Oxide Deposition Annealing for Neuromorphic Computing Applications

Author(s):  
Chun-Ling Hsu ◽  
Aftab Saleem ◽  
Amit Singh ◽  
Dayanand Kumar ◽  
Tseung-Yuen Tseng
1998 ◽  
Author(s):  
Tomasz Brozek ◽  
James Heddleson

Abstract Use of non-contact test techniques to characterize degradation of the Si-SiO2 system on the wafer surface exposed to a plasma environment have proven themselves to be sensitive and useful in investigation of plasma charging level and uniformity. The current paper describes application of the surface charge analyzer and surface photo-voltage tool to explore process-induced charging occurring during plasma enhanced chemical vapor deposition (PECVD) of TEOS oxide. The oxide charge, the interface state density, and dopant deactivation are studied on blanket oxidized wafers with respect to the effect of oxide deposition, power lift step, and subsequent annealing.


2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.


2013 ◽  
Author(s):  
Clare Thiem ◽  
Bryant Wysocki ◽  
Morgan Bishop ◽  
Nathan McDonald ◽  
James Bohl

2014 ◽  
Author(s):  
Bryant Wysocki ◽  
Nathan McDonald ◽  
Clare Thiem ◽  
Thomas Renz ◽  
James Bohl

2021 ◽  
Vol 42 (1) ◽  
pp. 010301
Author(s):  
Yanghao Wang ◽  
Yuchao Yang ◽  
Yue Hao ◽  
Ru Huang

ACS Nano ◽  
2020 ◽  
Author(s):  
Ya-Xin Hou ◽  
Yi Li ◽  
Zhi-Cheng Zhang ◽  
Jia-Qiang Li ◽  
De-Han Qi ◽  
...  

2021 ◽  
Author(s):  
Tao Zeng ◽  
Zhi Yang ◽  
Jiabing Liang ◽  
Ya Lin ◽  
Yankun Cheng ◽  
...  

Memristive devices are widely recognized as promising hardware implementations of neuromorphic computing. Herein, a flexible and transparent memristive synapse based on polyvinylpyrrolidone (PVP)/N-doped carbon quantum dot (NCQD) nanocomposites through regulating...


2021 ◽  
pp. 100393
Author(s):  
Bai Sun ◽  
Tao Guo ◽  
Guangdong Zhou ◽  
Shubham Ranjan ◽  
Yixuan Jiao ◽  
...  

2021 ◽  
pp. 2103672
Author(s):  
Jing Zhou ◽  
Tieyang Zhao ◽  
Xinyu Shu ◽  
Liang Liu ◽  
Weinan Lin ◽  
...  

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Batyrbek Alimkhanuly ◽  
Joon Sohn ◽  
Ik-Joon Chang ◽  
Seunghyun Lee

AbstractRecent studies on neural network quantization have demonstrated a beneficial compromise between accuracy, computation rate, and architecture size. Implementing a 3D Vertical RRAM (VRRAM) array accompanied by device scaling may further improve such networks’ density and energy consumption. Individual device design, optimized interconnects, and careful material selection are key factors determining the overall computation performance. In this work, the impact of replacing conventional devices with microfabricated, graphene-based VRRAM is investigated for circuit and algorithmic levels. By exploiting a sub-nm thin 2D material, the VRRAM array demonstrates an improved read/write margins and read inaccuracy level for the weighted-sum procedure. Moreover, energy consumption is significantly reduced in array programming operations. Finally, an XNOR logic-inspired architecture designed to integrate 1-bit ternary precision synaptic weights into graphene-based VRRAM is introduced. Simulations on VRRAM with metal and graphene word-planes demonstrate 83.5 and 94.1% recognition accuracy, respectively, denoting the importance of material innovation in neuromorphic computing.


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