Design of logical elements with single-event compensation for the 28-nm CMOS decoders

2016 ◽  
Author(s):  
Yuri V. Katunin ◽  
Vladimir Ya. Stenin ◽  
Artem V. Antonyuk
Keyword(s):  
Single Event ◽  
28 Nm

Single Event Upset Evaluation for a 28-nm FDSOI SRAM Type Buffer in an ARM Processor

2021 ◽  
Author(s):  
Shuting Shi ◽  
Rui Chen ◽  
Rui Liu ◽  
Mo Chen ◽  
Chen Shen ◽  
...  
Keyword(s):  
Single Event Upset ◽  
Single Event ◽  
Arm Processor ◽  
28 Nm

Investigation of single event effect in 28-nm system-on-chip with multi patterns

2020 ◽  
Vol 29 (10) ◽  
pp. 108504
Author(s):  
Wei-Tao Yang ◽  
Yong-Hong Li ◽  
Ya-Xin Guo ◽  
Hao-Yu Zhao ◽  
Yang Li ◽  
...  
Keyword(s):  
System On Chip ◽  
Single Event ◽  
Single Event Effect ◽  
On Chip ◽  
28 Nm

scholarly journals Research on temperature sensitivity of Single-event Transient pulse width in 28-nm bulk technology

2021 ◽  
Vol 2137 (1) ◽  
pp. 012031
Author(s):  
Bohan Zhang ◽  
Bin Liang ◽  
Yahao Fang
Keyword(s):  
Temperature Sensitivity ◽  
Pulse Width ◽  
Single Event ◽  
Single Event Transient ◽  
Worst Case ◽  
Deep Well ◽  
Influence Of Temperature On ◽  
Radiation Resistant ◽  
Bulk Technology ◽  
28 Nm

Abstract The influence of temperature on single-event transient (SET) pulse width has always been a hot issue in the field of anti-irradiation. Based on 3D-TCAD simulation, the temperature sensitivity of the SET pulse width of 28-nm bulk devices has been studied. The simulation results show that the electrical characteristics of the device shows an anti-temperature effect, but the worst case of SET pulse width still occurs at high temperature rather than low temperature. The influence of the triple-well structure on the temperature sensitivity of the SET pulse width has also been studied. The N+ deep well can significantly increase the SET pulse width when hitting NMOS device and enhance the temperature sensitivity of the SET pulse width. The research content of this article will provide reference for the design of radiation resistant chip.

scholarly journals Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

2020 ◽  
Vol 67 (7) ◽  
pp. 1461-1469 ◽  
Author(s):  
Juan Carlos Fabero ◽  
Hortensia Mecha ◽  
Francisco J. Franco ◽  
Juan Antonio Clemente ◽  
Golnaz Korkian ◽  
...  
Keyword(s):  
Single Event ◽  
Static Mode ◽  
Single Event Upsets ◽  
28 Nm

scholarly journals Single-Event Performance and Layout Optimization of Flip-Flops in a 28-nm Bulk Technology

2013 ◽  
Vol 60 (4) ◽  
pp. 2782-2788 ◽  
Author(s):  
K. Lilja ◽  
M. Bounasser ◽  
S.-J. Wen ◽  
R. Wong ◽  
J. Holst ◽  
...  
Keyword(s):  
Layout Optimization ◽  
Single Event ◽  
Bulk Technology ◽  
28 Nm

Electron-Induced Single-Event Upsets in 45-nm and 28-nm Bulk CMOS SRAM-Based FPGAs Operating at Nominal Voltage

2015 ◽  
Vol 62 (6) ◽  
pp. 2717-2724 ◽  
Author(s):  
Matthew J. Gadlage ◽  
Austin H. Roach ◽  
Adam R. Duncan ◽  
Mark W. Savage ◽  
Matthew J. Kay
Keyword(s):  
Single Event ◽  
Single Event Upsets ◽  
Nominal Voltage ◽  
28 Nm

scholarly journals Investigation of Heavy-Ion Induced Single-Event Transient in 28 nm Bulk Inverter Chain

Symmetry ◽  
2020 ◽  
Vol 12 (4) ◽  
pp. 624
Author(s):  
Anquan Wu ◽  
Bin Liang ◽  
Yaqing Chi ◽  
Zhenyu Wu
Keyword(s):  
Integrated Circuits ◽  
Heavy Ions ◽  
Heavy Ion ◽  
High Energy ◽  
Advanced Technology ◽  
Sensitive Volume ◽  
Single Event ◽  
Space Applications ◽  
Order Of Magnitude ◽  
28 Nm

The reliability of integrated circuits under advanced process nodes is facing more severe challenges. Single-event transients (SET) are an important cause of soft errors in space applications. The SET caused by heavy ions in the 28 nm bulk silicon inverter chains was studied. A test chip with good symmetry layout design was fabricated based on the 28 nm process, and the chip was struck by using 5 kinds of heavy ions with different linear energy transfer (LET) values on heavy-ion accelerator. The research results show that in advanced technology, smaller sensitive volume makes SET cross-section measured at 28 nm smaller than 65 nm by an order of magnitude, the lower critical charge required to generate SET will increase the reliability threat of low-energy ions to the circuit, and high-energy ions are more likely to cause single-event multiple transient (SEMT), which cannot be ignored in practical circuits. The transients pulse width data can be used as a reference for SET modeling in complex circuits.

scholarly journals Supply Voltage and Temperature Dependence of Single-Event Transient in 28-nm FDSOI MOSFETs

Symmetry ◽  
2019 ◽  
Vol 11 (6) ◽  
pp. 793 ◽  
Author(s):  
Jingyan Xu ◽  
Yang Guo ◽  
Ruiqiang Song ◽  
Bin Liang ◽  
Yaqing Chi
Keyword(s):  
Temperature Dependence ◽  
Temperature Effect ◽  
Pulse Width ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Single Event ◽  
Single Event Transient ◽  
Short Channel ◽  
28 Nm

Based on three-dimensional (3D) technology computer aided design (TCAD) simulations, the supply voltage and temperature dependence of single-event transient (SET) pulse width in 28-nm fully-depleted silicon-on-insulator (FDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated. FDSOI MOSFETs are symmetry devices with a superior control of the short channel effects (SCEs) and single-event effects (SEEs). Previous studies have suggested that the SET width is invariant when the temperature changes in FDSOI devices. Simulation results show that the SET pulse width increases as the supply voltage decreases. When the supply voltage is below 0.6 V, the SET pulse width increases sharply with the decrease of the supply voltage. The SET pulse width is not sensitive to temperature when the supply voltage is 1 V. However, when the supply voltage is 0.6 V or less, the SET pulse width exhibits an anti-temperature effect, and the anti-temperature effect is significantly enhanced as the supply voltage drops. Besides, the mechanism is analyzed from the aspects of saturation current and charge collection.

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