Clock separated logic: a double-rail latch circuit technique for high speed digital design

Author(s):  
T.S. Cheung ◽  
K. Asada
2012 ◽  
Vol 198-199 ◽  
pp. 1246-1249
Author(s):  
Sheng Hu Liu ◽  
Ya Min Xing

This electronic Logging while drilling (LWD) is a new sort of well drilling technology developed in recent years. As to the traditional cable borehole survey, the LWD method has many advantages because of its higher accuracy, higher geologic strata resolution capacity, much less time and cost. To meet the current logging technology needs, A data acquisition and processing system for logging while drilling is designed.It minutely introduces the collection system structure, acquisition Program, the digital design of LWD and discusses the design and the implementation of each functional module.The system which designed on the basis of the high precise DSP and FPGA implements signal pretreatment, high speed A/D control and digitalization of the phase sensitive demodulation etc, optimizes the acquisition and processing system and supplies a new way for the development of logging while drilling.Experimental results show that system performance has attained the design requirement.


2011 ◽  
Vol 337 ◽  
pp. 46-49
Author(s):  
Li Hua Song ◽  
Jun Yuan Kang

In accordance with the latest development direction in the filed of strengthening the heat transfer technology of strengthening the heat transfer on division of strengthening heat transfer by international authoritative Professor A.E. Bergle), including 3D(three-dimensional) heat transfer of ultra-high performance improved in the fins of the design and analysis; 3D heat transfer strengthening of the plowing process mechanism the flexibility ,high speed and high precision of gathered tools and the realization of a 3D digital design and manufacturing . It also researches on the influential law of process parameters on the formation of the fin. It is shown that the whole fin-forming process can be classified into three stages:plowing,heaving and fins forming, and that the front angle,plowing depth and the plowing speed are the main factors influencing the fin forming. Moreover,within a certain range,the height of fin increases with the front angle and the plowing depth.


2021 ◽  
Vol 12 (2) ◽  
pp. 63-73
Author(s):  
N. A. Avdeev ◽  
◽  
P. N. Bibilo ◽  

The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power con­sumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.


2014 ◽  
Vol 526 ◽  
pp. 351-356
Author(s):  
Li Xi Yue ◽  
Jian Hui Zhou ◽  
Yan Nan Lu ◽  
Chong Chong Ji ◽  
Zhi Yong Yu

The dissertation deals with some key issues relevant to the controller design and digital design method for a newly patented high-speed parallel manipulator. Meanwhile, a Virtual Prototyping based co-simulation platform is also established according to the ADAMS and Matlab/Simulink software. In order to promote the ability that the manipulator traces the prescribed trajectory, a model based computed torque controller is described in detail, and a neural network algorithm is also used to optimize controller parameters real-timely under the consideration of systematic nonlinear, modeling error and outer disturbance. The neural network based computed torque controller increases the robustness of system dramatically.


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