10-Gb/s driver amplifier using a tapered gate line for improved input matching

2005 ◽  
Vol 53 (10) ◽  
pp. 3115-3120 ◽  
Author(s):  
J. Shohat ◽  
I.D. Robertson ◽  
S.J. Nightingale
Author(s):  
Leonardo Zappelli

AbstractNowadays, the design of dividers is based on electromagnetic software that optimizes some geometric parameters to obtain the required performance. The choice of the geometry of the discontinuities contained in the divider and of the optimization initial point is quite critical to satisfy the divider requirements. In the last years, it is quite rare to find in the literature a theoretical approach helping the designers in the choice of the divider geometry. Helpful suggestion can derive by the analysis of the electric field in a trial divider that satisfies power division among the output ports in a thin band. In fact, the electric field null can be filled with metallic septa that ensure the same behavior at any frequency. The optimization of the septa position/form with numerical electromagnetic software permits to obtain divider with large bandwidth. A further analysis of the electric field null in the divider permits to add lateral metallic septa that further enlarge the transmission band. Finally, the design of an input matching network increases the transmitted power to the desired value.


Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 780
Author(s):  
Matteo D’Addato ◽  
Alessia M. Elgani ◽  
Luca Perilli ◽  
Eleonora Franchi Scarselli ◽  
Antonio Gnudi ◽  
...  

This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to Nm = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10−3 missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the Nm ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups.


2012 ◽  
Vol 33 (12) ◽  
pp. 125011
Author(s):  
Geliang Yang ◽  
Zhigong Wang ◽  
Zhiqun Li ◽  
Qin Li ◽  
Zhu Li ◽  
...  

2013 ◽  
Vol 479-480 ◽  
pp. 1014-1017
Author(s):  
Yi Cheng Chang ◽  
Meng Ting Hsu ◽  
Yu Chang Hsieh

In this study, three stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. The UWB LNA is design in 0.18μm TSMC CMOS technique. The LNA input and output return loss are both less than-10dB, and achieved 10dB of average power gain, the minimum noise figure is 6.55dB, IIP3 is about-9.5dBm. It consumes 11mW from a 1.0-V supply voltage.


2013 ◽  
Vol 2013 ◽  
pp. 1-5 ◽  
Author(s):  
Ahmed Ragheb ◽  
Ghazal Fahmy ◽  
Iman Ashour ◽  
Abdel Hady Ammar

This paper presents a design of a reconfigurable low noise amplifier (LNA) for multiband orthogonal frequency division multiplexing (MB-OFDM) ultra wideband (UWB) receivers. The proposed design is divided into three stages; the first one is a common gate (CG) topology to provide the input matching over a wideband. The second stage is a programmable circuit to control the mode of operation. The third stage is a current reuse topology to improve the gain, flatness and consume lower power. The proposed LNA is designed using 0.18 μm CMOS technology. This LNA has been designed to operate in two subbands of MB-OFDM UWB, UWB mode-1 and mode-3, as a single or concurrent mode. The simulation results exhibit the power gain up to 17.35, 18, and 11 dB for mode-1, mode-3, and concurrent mode, respectively. The NF is 3.5, 3.9, and 6.5 and the input return loss is better than −12, −13.57, and −11 dB over mode-1, mode-3, and concurrent mode, respectively. This design consumes 4 mW supplied from 1.2 V.


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