A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology

2011 ◽  
Vol 19 (9) ◽  
pp. 1718-1722 ◽  
Author(s):  
Won-Joo Yun ◽  
Hyun-Woo Lee ◽  
Dongsuk Shin ◽  
Suki Kim
Keyword(s):  
Cmos Technology ◽  
Low Jitter

A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13μm CMOS technology

2008 ◽  
Author(s):  
Yu-Hao Hsu ◽  
Ming-Hao Lu ◽  
Ping-Lin Yang ◽  
Fan-Ta Chen ◽  
You-Hung Li ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Low Jitter

A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

2011 ◽  
Vol 32 (3) ◽  
pp. 035004 ◽  
Author(s):  
Niansong Mei ◽  
Yu Sun ◽  
Bo Lu ◽  
Yaohua Pan ◽  
Yumei Huang ◽  
...  
Keyword(s):  
Phase Locked Loop ◽  
Cmos Technology ◽  
Low Jitter

A low jitter 2.7mW/Gbps 180Gb/s 12-lane transmitter in a 40nm CMOS technology

2012 ◽  
Author(s):  
Kamran Farzan ◽  
Mehrdad Ramezani ◽  
Angus McLaren ◽  
Roman Pahuta ◽  
Nadeesha Amarasinghe ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Low Jitter

scholarly journals A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop

VLSI Design ◽  
2000 ◽  
Vol 11 (2) ◽  
pp. 107-113
Author(s):  
Chua-Chin Wang ◽  
Yu-Tsun Chien ◽  
Ying-Pei Chen
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Phase Locked Loops ◽  
Digital Cmos ◽  
Display Devices ◽  
Noise Coupling ◽  
Signal Systems ◽  
Supply Noise ◽  
Low Jitter ◽  
Rc Circuit

In high-speed digital systems and high-resolution display devices, the jitter effect of phase-locked loops (PLL) limits the system performance. Power supply noise coupling is one of the major causes of PLL jitter problems, especially with mixed-signal systems. The paper presents a targeted 5.0V 500 MHz PLL which is implemented by a 0.6 um 1P3M digital CMOS technology. The features of the proposed design include a load-optimized 3-stage VCO, a frequency limiter RC circuit, and a ratioed VCO controlling current mirror. The jitter, thus, is reduced to 72.693 ps at 600 MHz at the presence of supply noise, while the sensitivity is limited to 286.6 ps/V. This high-noise immunity design allows that the PLL can be integrated with digital circuits.

A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology

2010 ◽  
Vol 31 (1) ◽  
pp. 015001 ◽  
Author(s):  
Chen Hu ◽  
Lu Bo ◽  
Shao Ke ◽  
Xia Lingli ◽  
Huang Yumei ◽  
...  
Keyword(s):  
Phase Locked Loop ◽  
Cmos Technology ◽  
Low Jitter

A Low-Jitter Low-Phase-Noise 10-GHz Sub-Harmonically Injection-Locked PLL With Self-Aligned DLL in 65-nm CMOS Technology

2014 ◽  
Vol 62 (3) ◽  
pp. 543-555 ◽  
Author(s):  
Hong-Yeh Chang ◽  
Yen-Liang Yeh ◽  
Yu-Cheng Liu ◽  
Meng-Han Li ◽  
Kevin Chen
Keyword(s):  
Phase Noise ◽  
Cmos Technology ◽  
Low Jitter ◽  
Low Phase Noise
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