A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

2011 ◽  
Vol 32 (3) ◽  
pp. 035004 ◽  
Author(s):  
Niansong Mei ◽  
Yu Sun ◽  
Bo Lu ◽  
Yaohua Pan ◽  
Yumei Huang ◽  
...  
Keyword(s):  
Phase Locked Loop ◽  
Cmos Technology ◽  
Low Jitter

A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology

2010 ◽  
Vol 31 (1) ◽  
pp. 015001 ◽  
Author(s):  
Chen Hu ◽  
Lu Bo ◽  
Shao Ke ◽  
Xia Lingli ◽  
Huang Yumei ◽  
...  
Keyword(s):  
Phase Locked Loop ◽  
Cmos Technology ◽  
Low Jitter

scholarly journals A Low Jitter – Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer Cmos Technology

2019 ◽  
Vol 8 (4) ◽  
pp. 3994-3999
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
High Speed ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Critical Parameters ◽  
Nanometer Cmos ◽  
Dc Power ◽  
Low Jitter ◽  
Low Phase Noise

For high speed communication applications; jitter, phase noise and power consumption are most critical parameters required to be considered for PLL designs. A sub harmonically injection locking concept can be used in PLL to reduce jitter and phase noise. Such design is very effective for high frequency applications. This article presents similar design for 7.5-GHz Phase locked loop in 180 nm CMOS technology. The measured phase noise of the proposed PLL with self aligned injection at 1 MHz offset is 121.14 dBc/Hz and rms jitter is 110 fs. The total dc power consumption is 13.99 mW. To support the claim process variation with design corner analysis using random variations are carried out.

scholarly journals A low jitter all - digital phase - locked loop in 180 nm CMOS technology

2016 ◽  
Vol 675 (4) ◽  
pp. 042042
Author(s):  
O V Shumkin ◽  
V A Butuzov ◽  
D D Normanov ◽  
P Yu Ivanov
Keyword(s):  
Phase Locked Loop ◽  
Cmos Technology ◽  
Digital Phase ◽  
Low Jitter

A Novel Time-to-Digital Converter Based on Low-Jitter Phase-Locked Loop

2017 ◽  
Vol 63 (3) ◽  
pp. 336-345
Author(s):  
Jin Wu ◽  
Chao Wang ◽  
Shu-fang Shi ◽  
Xiang-rong Yu ◽  
Li-xia Zheng ◽  
...  
Keyword(s):  
Phase Locked Loop ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Low Jitter

scholarly journals 10Ghz Charge Pump PLL for Low Jitter Applica-tions

2018 ◽  
Vol 7 (2.12) ◽  
pp. 348
Author(s):  
Rajeshwari D S ◽  
P V Rao ◽  
Ramesh Karmungi
Keyword(s):  
Charge Pump ◽  
Phase Locked Loop ◽  
Frequency Divider ◽  
Differential Delay ◽  
Turn On ◽  
Delay Cell ◽  
Start Up ◽  
Charge Pump Pll ◽  
Low Jitter ◽  
Symmetric Load

This paper presents design and simulation of charge pump architectures for 10GHz Charge Pump Phase locked Loop. Differential delay cell VCO with symmetric load and Programmable frequency divider are efficiently implemented in loop. Able to achieve Peak jitter of the Divider 10ns, Peak jitter of VCO 205ps at 1GHz.Charge pump is analysed in loop by reduced current mismatch using improved high swing cascode structure including start up circuitand it has low turn ON voltage and high ouput impedance to provide stable voltage.Charge pump results current mismatch less than 0.05%.10GHz DPLL is simulated with 65nm techonology, 1.2V and tsmc foundary model files

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

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