scholarly journals Signal Conditioning ASIC for the Detection of Combustible Gases

2021 ◽  
Author(s):  
Shelja Kaushal ◽  
Ashwani K. Rana
Keyword(s):  
Power Consumption ◽  
Operating Temperature ◽  
Cmos Technology ◽  
Low Noise ◽  
Working Environment ◽  
Voltage Controlled Oscillator ◽  
Signal Conditioning ◽  
Control Room ◽  
Zero Crossing ◽  
Gas Concentration

In this paper, the signal conditioning ASIC has been designed for transferring the information regarding gas concentration from the hazardous environment of coal mines to the control room. The ASIC is designed to avoid danger in the hazardous working environment with features like high operating temperature, faster response, high sensitivity, and low power consumption. For the desired application, the different modules for ASIC including Low Noise Amplifier (LNA), Voltage Controlled Oscillator (VCO), and Zero Crossing Detector integrated with a buffer are designed based on 180nm CMOS technology node using SCL pdk files on Cadence Virtuoso tool. The overall power consumption of the designed ASIC is 3.92mW with a gain of ~15 and a frequency range of 10KHz to 200KHz for 0.1% gas concentration for a sensor with the operating temperature of ~150oC. The final output of the ASIC is 0V to 1.8V of the square wave which can be further transmitted to the control room.

scholarly journals Design of a very low-power, low-cost 60 GHz receiver front-end implemented in 65 nm CMOS technology

2011 ◽  
Vol 3 (2) ◽  
pp. 131-138 ◽  
Author(s):  
Michael Kraemer ◽  
Daniela Dragomirescu ◽  
Robert Plana
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Noise Figure ◽  
Low Cost ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
60 Ghz ◽  
Front End

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

Power Efficient Implementation of Low Noise CMOS LC VCO using 32nm Technology for RF Applications

2018 ◽  
Vol 6 (8) ◽  
pp. 53
Author(s):  
Shitesh Tiwari ◽  
Sumant Katiyal ◽  
Parag Parandkar
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Tuning Range ◽  
Low Voltage ◽  
Performance Comparison ◽  
Low Noise ◽  
Center Frequency ◽  
Voltage Controlled Oscillator ◽  
Low Phase Noise ◽  
Lc Vco

Voltage Controlled Oscillator (VCO) is an integral component of most of the receivers such as GSM, GPS etc. As name indicates, oscillation is controlled by varying the voltage at the capacitor of LC tank. By varying the voltage, VCO can generate variable frequency of oscillation. Different VCO Parameters are contrasted on the basis of phase noise, tuning range, power consumption and FOM. Out of these phase noise is dependent on quality factor, power consumption, oscillation frequency and current. So, design of LC VCO at low power, low phase noise can be obtained with low bias current at low voltage.  Nanosize transistors are also contributes towards low phase noise. This paper demonstrates the design of low phase noise LC VCO with 4.89 GHz tuning range from 7.33-11.22 GHz with center frequency at 7 GHz. The design uses 32nm technology with tuning voltage of 0-1.2 V. A very effective Phase noise of -114 dBc / Hz is obtained with FOM of -181 dBc/Hz. The proposed work has been compared with five peer LC VCO designs working at higher feature sizes and outcome of this performance comparison dictates that the proposed work working at better 32 nm technology outperformed amongst others in terms of achieving low Tuning voltage and moderate FoM, overshadowed by a little expense of power dissipation. 

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

scholarly journals A Low-Power Opamp-Less Second-Order Delta-Sigma Modulator for Bioelectrical Signals in 0.18 µm CMOS

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6456
Author(s):  
Fernando Cardes ◽  
Nikhita Baladari ◽  
Jihyun Lee ◽  
Andreas Hierlemann
Keyword(s):  
Low Power ◽  
Low Frequency ◽  
Cmos Technology ◽  
Low Noise ◽  
Second Order ◽  
Frequency Noise ◽  
Voltage Controlled Oscillator ◽  
Noise Shaping ◽  
Delta Sigma Modulator ◽  
Delta Sigma

This article reports on a compact and low-power CMOS readout circuit for bioelectrical signals based on a second-order delta-sigma modulator. The converter uses a voltage-controlled, oscillator-based quantizer, achieving second-order noise shaping with a single opamp-less integrator and minimal analog circuitry. A prototype has been implemented using 0.18 μm CMOS technology and includes two different variants of the same modulator topology. The main modulator has been optimized for low-noise, neural-action-potential detection in the 300 Hz–6 kHz band, with an input-referred noise of 5.0 μVrms, and occupies an area of 0.0045 mm2. An alternative configuration features a larger input stage to reduce low-frequency noise, achieving 8.7 μVrms in the 1 Hz–10 kHz band, and occupies an area of 0.006 mm2. The modulator is powered at 1.8 V with an estimated power consumption of 3.5 μW.

scholarly journals Power Efficient, Low Noise 2-5 GHz Phase Locked Loop

2011 ◽  
Vol 16 (4) ◽  
pp. 66-72
Author(s):  
V.Sh. Melikyan ◽  
A.A. Durgaryan ◽  
H.P. Petrosyan ◽  
A.G. Stepanyan
Keyword(s):  
Power Consumption ◽  
Efficient Solution ◽  
Phase Locked Loop ◽  
Low Noise ◽  
System Level ◽  
Voltage Controlled Oscillator ◽  
Power Efficient ◽  
Area Overhead ◽  
Output Noise ◽  
5 Ghz

A power and noise efficient solution for phase locked loop (PLL) is presented. A lock detector is implemented to deactivate the PLL components, except the voltage controlled oscillator (VCO), in the locked state. Signals deactivating/activating the PLL are discussed on system level. The introduced technique significantly saves power and decreases PLL output jitter. As a result whole PLL power consumption and output noise decreased about 35-38% in expense of approximately 17% area overhead

scholarly journals An efficient design of 45-nm CMOS low-noise charge sensitive amplifier for wireless receivers

2022 ◽  
Vol 12 (2) ◽  
pp. 1274
Author(s):  
Islam T. Almalkawi ◽  
Ashraf H. Al-Bqerat ◽  
Awni Itradat ◽  
Jamal N. Al-Karaki
Keyword(s):  
Power Consumption ◽  
Signal To Noise Ratio ◽  
Cmos Technology ◽  
Channel Length ◽  
Low Noise ◽  
Efficient Design ◽  
Wireless Devices ◽  
Noise Spectral Density ◽  
Wireless Applications ◽  
Amplifier Design

<p>Amplifiers are widely used in signal receiving circuits, such as antennas, medical imaging, wireless devices and many other applications. However, one of the most challenging problems when building an amplifier circuit is the noise, since it affects the quality of the intended received signal in most wireless applications. Therefore, a preamplifier is usually placed close to the main sensor to reduce the effects of interferences and to amplify the received signal without degrading the signal-to-noise ratio. Although different designs have been optimized and tested in the literature, all of them are using larger than 100 nm technologies which have led to a modest performance in terms of equivalent noise charge (ENC), gain, power consumption, and response time. In contrast, we consider in this paper a new amplifier design technology trend and move towards sub 100 nm to enhance its performance. In this work, we use a pre-well-known design of a preamplifier circuit and rebuild it using 45 nm CMOS technology, which is made for the first time in such circuits. Performance evaluation shows that our proposed scaling technology, compared with other scaling technology, extremely reduces ENC of the circuit by more than 95%. The noise spectral density and time resolution are also reduced by 25% and 95% respectively. In addition, power consumption is decreased due to the reduced channel length by 90%. As a result, all of those enhancements make our proposed circuit more suitable for medical and wireless devices.</p>

scholarly journals Non-Linear Mathematical Modelling for Phase Locked Loop

2018 ◽  
Vol 7 (4.10) ◽  
pp. 81
Author(s):  
Prithiviraj R ◽  
Selvakumar J
Keyword(s):  
High Speed ◽  
Linear Models ◽  
Low Cost ◽  
Phase Error ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Low Noise ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Non Linear

Design of Phase Locked Loop (PLL) plays a vital role in transceiver field. Phase Locked Loop comprises of three blocks, namely Phase and frequency detector, loop filter and voltage-controlled oscillator. The greater advancements in CMOS technology such as high frequency, high speed, low noise and phase error leads to low-cost PLL This work aims to develop higher order non-linear models of general Phase Locked Loop. The condition of stability and choice of loop filter is also determined. Based on the analysis, the transfer function for PLL is determined.  

A VERY LOW NOISE WIDEBAND CLASS-C CMOS LC VCO

2012 ◽  
Vol 21 (04) ◽  
pp. 1250033 ◽  
Author(s):  
FATEMEH ATAEI ◽  
MOHAMMAD YAVARI
Keyword(s):  
Phase Noise ◽  
Tuning Range ◽  
Capacitor Bank ◽  
Cmos Technology ◽  
Low Noise ◽  
Voltage Controlled Oscillator ◽  
Switching Scheme ◽  
Wide Tuning Range ◽  
New Class ◽  
Class C

In this paper, a new class-C voltage-controlled oscillator (VCO) is presented. In the proposed VCO, the tail capacitor of the conventional class-C oscillator is dislocated from the source of the cross-coupled transistors to their gate to achieve a rail-to-rail output swing. This improves the phase noise by 2.9 dB compared to the conventional class-C one. Besides, a new switching scheme is presented in the switched capacitor bank used for coarse tuning of the proposed VCO to lower the on resistance of the switches as well as to reduce the parasitic capacitors. This wide tuning range class-C VCO is designed in a 0.18 μm CMOS technology. It achieves a -125.3 dBc/Hz phase noise at 1 MHz offset from a 2.2 GHz carrier frequency while covering a wide tuning range from 1.82 to 2.65 GHz and consuming 3.5 mW power from a single 0.9 V power supply.

scholarly journals Design, Analysis and Measurement Results of a Fully-Integrated Low-power LNA Presenting Faults

2013 ◽  
Vol 8 (1) ◽  
pp. 32-42
Author(s):  
Paulo M. Moreira e Silva ◽  
Fernando Rangel de Sousa
Keyword(s):  
Power Consumption ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Fully Integrated ◽  
Uncertainty Sources ◽  
Measurement Results ◽  
Noise Amplifier ◽  
A Current ◽  
Measured Input

We present in this paper the analysis, design and measurement results of a low noise amplifier (LNA) operating in the ISM band at 2.45 GHz. The circuit topology adopted was based on a current reuse technique to minimize the power consumption. A prototype was fabricated in a 0.18-μm standard CMOS technology and the measured power consumption was 1.1 mW. The measured input reflection coefficient was below -10 dB and the reverse isolation was higher than 20 dB. The measured insertion gain and noise figure were 5.6 dB and 4.8 dB respectively, with divergences from the simulated values of 5 dB and 2 dB, respectively. To explain these discrepancies, we devised an analysis on the circuit, including sources of uncertainties. Moreover, we characterized a transistor included in the LNA die, that helped to explain part of the disagreements. After including the uncertainty sources, we wereaable to explain a deviation of 3.9 dB in the insertion gain with respect to the simulated result.

scholarly journals A LOW PHASE NOISE, POWER EFFICIENT VOLTAGE CONTROLLED OSCILLATOR USING 0.18-μM CMOS TECHNOLOGY

2014 ◽  
pp. 256-259
Author(s):  
AJIT SAMASGIKAR
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Tuning Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Noise Power ◽  
Voltage Controlled Oscillator ◽  
Power Efficient ◽  
Sustained Oscillations ◽  
Low Phase Noise

A low phase noise, power efficient VCO using UMC 0.18μm CMOS technology has been proposed in this paper. The proposed VCO has a tuning range of 9.71GHz to 9.9GHz, with a phase noise of -79.88 dBc/Hz @ 600kHz offset. The Vtune ranging between 1V - 1.5V generates sustained oscillations. The maximum power consumption of the VCO is 11.9mW using a supply voltage of 1.8V with ±10% variation.

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