Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit Against False Trigger During Fast Power-ON Events

2021 ◽  
Author(s):  
Han-Sheng Huang ◽  
Ming-Dou Ker
Keyword(s):  
Fast Power

A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation

2013 ◽  
Vol E96.A (12) ◽  
pp. 2533-2541
Author(s):  
Daisuke FUJIMOTO ◽  
Toshihiro KATASHITA ◽  
Akihiko SASAKI ◽  
Yohei HORI ◽  
Akashi SATOH ◽  
...  
Keyword(s):  
Vlsi Circuits ◽  
Side Channel ◽  
Side Channel Attack ◽  
Fast Power

Fast power rectifier design using local lifetime and emitter efficiency control techniques

1999 ◽  
Vol 30 (6) ◽  
pp. 505-512 ◽  
Author(s):  
Ettore Napoli ◽  
Antonio G.M Strollo ◽  
Paolo Spirito
Keyword(s):  
Control Techniques ◽  
Efficiency Control ◽  
Fast Power ◽  
Power Rectifier

Design of finite-time guidance law based on observer and head-pursuit theory

2021 ◽  
pp. 095441002098456
Author(s):  
Chenqi Zhu
Keyword(s):  
Finite Time ◽  
Three Dimensional ◽  
Hypersonic Vehicle ◽  
Two Dimensional ◽  
Dimensional Model ◽  
Reaching Law ◽  
Guidance Law ◽  
Fast Power ◽  
Simulation Results ◽  
Guidance Laws

In order to improve the guiding accuracy in intercepting the hypersonic vehicle, this article presents a finite-time guidance law based on the observer and head-pursuit theory. First, based on a two-dimensional model between the interceptor and target, this study applies the fast power reaching law to head-pursuit guidance law so that it can alleviate the chattering phenomenon and ensure the convergence speed. Second, target maneuvers are considered as system disturbances, and the head-pursuit guidance law based on an observer is proposed. Furthermore, this method is extended to a three-dimensional case. Finally, comparative simulation results further verify the superiority of the guidance laws designed in this article.

scholarly journals Fast Power Density Assessment of 5G Mobile Handset Using Equivalent Currents Method

2021 ◽  
pp. 1-1
Author(s):  
Wang He ◽  
Bo Xu ◽  
Lucia Scialacqua ◽  
Zhinong Ying ◽  
Alessandro Scannavini ◽  
...  
Keyword(s):  
Power Density ◽  
Fast Power ◽  
Mobile Handset ◽  
Density Assessment ◽  
Equivalent Currents

scholarly journals A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 177
Author(s):  
Dongjun Park ◽  
Sungwook Choi ◽  
Jongsun Kim
Keyword(s):  
Sampling Technique ◽  
Cmos Process ◽  
Detection Range ◽  
Delay Locked Loop ◽  
Delta Sigma Modulator ◽  
Correlated Double Sampling ◽  
Delta Sigma ◽  
Fast Power ◽  
Low Jitter ◽  
Reference Clock

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

A 5 Gb/s, 10 ns Power-On-Time, 36 $\mu$W Off-State Power, Fast Power-On Transmitter for Energy Proportional Links

2014 ◽  
Vol 49 (10) ◽  
pp. 2243-2258 ◽  
Author(s):  
Tejasvi Anand ◽  
Amr Elshazly ◽  
Mrunmay Talegaonkar ◽  
Brian Young ◽  
Pavan Kumar Hanumolu
Keyword(s):  
State Power ◽  
Fast Power
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