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A novel memory cell architecture for high-density DRAMs
Symposium on VLSI Circuits
◽
10.1109/vlsic.1989.1037509
◽
1989
◽
Cited By ~ 6
Author(s):
Ohta
◽
Mimoto
◽
Torimaru
◽
Miyake
Keyword(s):
Memory Cell
◽
High Density
◽
Cell Architecture
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References
Highly Extendible Memory Cell Architecture for Reliable Data Retention Time for 0.10mm Technology Node and beyond
32nd European Solid-State Device Research Conference
◽
10.1109/essderc.2002.194995
◽
2002
◽
Cited By ~ 2
Author(s):
J. Lee
◽
C. Cho
◽
J. Lee
◽
S. Shin
◽
J.-W. Lee
◽
...
Keyword(s):
Retention Time
◽
Memory Cell
◽
Reliable Data
◽
Data Retention
◽
Technology Node
◽
Cell Architecture
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A Study on High Density Gate-Oxide Anti-Fuse PROM Memory Cell Program Features
MATEC Web of Conferences
◽
10.1051/matecconf/20167510004
◽
2016
◽
Vol 75
◽
pp. 10004
Author(s):
Keqin Yang
◽
Suge Yue
◽
Shijin Lu
Keyword(s):
Memory Cell
◽
Gate Oxide
◽
High Density
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Novel SONOS and Floating-Gate Flash Memory Cell Structures for High Density and High Reliability Applications
ECS Meeting Abstracts
◽
10.1149/ma2007-02/25/1296
◽
2007
◽
Keyword(s):
Flash Memory
◽
High Reliability
◽
Memory Cell
◽
High Density
◽
Floating Gate
◽
Cell Structures
◽
Flash Memory Cell
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Ag Ionic Memory Cell Technology for Terabit-Scale High-Density Application
2019 Symposium on VLSI Technology
◽
10.23919/vlsit.2019.8776568
◽
2019
◽
Cited By ~ 2
Author(s):
Shosuke Fujii
◽
Reika Ichihara
◽
Takuya Konno
◽
Marina Yamaguchi
◽
Harumi Seki
◽
...
Keyword(s):
Memory Cell
◽
High Density
◽
Cell Technology
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A trimless, 0.5V–1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access
IEEE Asian Solid-State Circuits Conference 2011
◽
10.1109/asscc.2011.6123627
◽
2011
◽
Cited By ~ 5
Author(s):
K. Kushida
◽
O. Hirabayashi
◽
F. Tachibana
◽
H. Hara
◽
A. Kawasumi
◽
...
Keyword(s):
Memory Cell
◽
High Density
◽
Dynamic Cell
◽
Cell Stability
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Multi-step word-line control technology in hierarchical cell architecture for scaled-down high-density SRAMs
2010 Symposium on VLSI Circuits
◽
10.1109/vlsic.2010.5560336
◽
2010
◽
Cited By ~ 19
Author(s):
K. Takeda
◽
T. Saito
◽
S. Asayama
◽
Y. Aimoto
◽
H. Kobatake
◽
...
Keyword(s):
High Density
◽
Control Technology
◽
Cell Architecture
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Programming dynamics of a single electron memory cell with a high-density SiGe nanocrystal array at room temperature
1999 57th Annual Device Research Conference Digest (Cat. No.99TH8393)
◽
10.1109/drc.1999.806350
◽
2003
◽
Cited By ~ 2
Author(s):
Dong-Hyuk Chae
◽
Tae-Sik Yoon
◽
Dae Hwan Kim
◽
Jang-Yeon Kwon
◽
Ki-Bum Kim
◽
...
Keyword(s):
Room Temperature
◽
Memory Cell
◽
High Density
◽
Single Electron
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Acknowledgment of support to Yang, X., Cai, L., Huang, H. and Zhao, X. (2011), A comparative analysis and design of quantum-dot cellular automata memory cell architecture. International Journal of Circuit Theory and Applications. doi: 10.1002/cta.710
International Journal of Circuit Theory and Applications
◽
10.1002/cta.828
◽
2012
◽
Vol 40
(1)
◽
pp. 105-105
Author(s):
Xiaokuo Yang
◽
Li Cai
◽
Hongtu Huang
◽
Xiaohui Zhao
Keyword(s):
Comparative Analysis
◽
Cellular Automata
◽
Quantum Dot
◽
Memory Cell
◽
Circuit Theory
◽
Quantum Dot Cellular Automata
◽
Analysis And Design
◽
Cell Architecture
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A high-density dual-port memory cell operation and array architecture for ULSI DRAMs
IEEE Journal of Solid-State Circuits
◽
10.1109/4.126551
◽
1992
◽
Vol 27
(4)
◽
pp. 610-617
◽
Cited By ~ 5
Author(s):
H. Hidaka
◽
K. Arimoto
◽
K. Fujishima
Keyword(s):
Memory Cell
◽
High Density
◽
Array Architecture
Download Full-text
A New High-Density Twin-Gate Isolation One-Time Programmable Memory Cell in Pure 28-nm CMOS Logic Process
IEEE Transactions on Electron Devices
◽
10.1109/ted.2014.2371617
◽
2015
◽
Vol 62
(1)
◽
pp. 121-127
◽
Cited By ~ 8
Author(s):
Woan Yun Hsiao
◽
Ping Chun Peng
◽
Tzong-Sheng Chang
◽
Yu-Der Chih
◽
Wu-Chin Tsai
◽
...
Keyword(s):
Memory Cell
◽
High Density
◽
Logic Process
◽
28 Nm
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