Programming dynamics of a single electron memory cell with a high-density SiGe nanocrystal array at room temperature

2003 ◽  
Author(s):  
Dong-Hyuk Chae ◽  
Tae-Sik Yoon ◽  
Dae Hwan Kim ◽  
Jang-Yeon Kwon ◽  
Ki-Bum Kim ◽  
...  
Keyword(s):  
Room Temperature ◽  
Memory Cell ◽  
High Density ◽  
Single Electron

Si Nanocrystal Memory Cell with Room-Temperature Single Electron Effects

2001 ◽  
Vol 40 (Part 1, No. 2A) ◽  
pp. 447-451 ◽  
Author(s):  
Ilgweon Kim ◽  
Sangyeon Han ◽  
Kwangseok Han ◽  
Jongho Lee ◽  
Hyungcheol Shin
Keyword(s):  
Room Temperature ◽  
Memory Cell ◽  
Single Electron ◽  
Si Nanocrystal ◽  
Nanocrystal Memory ◽  
Electron Effects

scholarly journals Single-Electron Memories

VLSI Design ◽  
1998 ◽  
Vol 8 (1-4) ◽  
pp. 219-223 ◽  
Author(s):  
Christoph Wasshuber ◽  
Hans Kosina ◽  
Siegfried Selberherr
Keyword(s):  
Power Consumption ◽  
Room Temperature ◽  
State Of The Art ◽  
Memory Cell ◽  
Single Electron ◽  
Lower Power ◽  
Memory Chip ◽  
Single Electronics ◽  
Background Charge ◽  
Random Background

One of the most promising applications of single-electronics is a single-electron memory chip. Such a chip would have orders of magnitude lower power consumption compared to state-of-the-art dynamic memories, and would allow integration densities beyond the tera bit chip.We studied various single-electron memory designs. Additionally we are proposing a new memory cell which we call the T-memory cell. This cell can be manufactured with state-of-the-art lithography, it operates at room temperature and shows a strong resistance against random background charge.

scholarly journals Silicon single-electron random number generator based on random telegraph signals at room temperature

AIP Advances ◽  
2020 ◽  
Vol 10 (11) ◽  
pp. 115101
Author(s):  
Kouta Ibukuro ◽  
Fayong Liu ◽  
Muhammad Khaled Husain ◽  
Moïse Sotto ◽  
Joseph Hillier ◽  
...  
Keyword(s):  
Room Temperature ◽  
Random Number ◽  
Random Number Generator ◽  
Single Electron ◽  
Number Generator ◽  
Random Telegraph Signals

scholarly journals Experimental and Numerical Investigation of the ECAP Processed Copper: Microstructural Evolution, Crystallographic Texture and Hardness Homogeneity

Metals ◽  
2021 ◽  
Vol 11 (4) ◽  
pp. 607
Author(s):  
A. I. Alateyah ◽  
Mohamed M. Z. Ahmed ◽  
Yasser Zedan ◽  
H. Abd El-Hafez ◽  
Majed O. Alawad ◽  
...  
Keyword(s):  
Grain Size ◽  
Equal Channel Angular Pressing ◽  
Cross Section ◽  
Room Temperature ◽  
Pure Copper ◽  
High Density ◽  
Ecap Processing ◽  
Heterogeneous Distribution ◽  
Angular Pressing ◽  
Average Grain Size

The current study presents a detailed investigation for the equal channel angular pressing of pure copper through two regimes. The first was equal channel angular pressing (ECAP) processing at room temperature and the second was ECAP processing at 200 °C for up to 4-passes of route Bc. The grain structure and texture was investigated using electron back scattering diffraction (EBSD) across the whole sample cross-section and also the hardness and the tensile properties. The microstructure obtained after 1-pass at room temperature revealed finer equiaxed grains of about 3.89 µm down to submicrons with a high density of twin compared to the starting material. Additionally, a notable increase in the low angle grain boundaries (LAGBs) density was observed. This microstructure was found to be homogenous through the sample cross section. Further straining up to 2-passes showed a significant reduction of the average grain size to 2.97 µm with observable heterogeneous distribution of grains size. On the other hand, increasing the strain up to 4-passes enhanced the homogeneity of grain size distribution. The texture after 4-passes resembled the simple shear texture with about 7 times random. Conducting the ECAP processing at 200 °C resulted in a severely deformed microstructure with the highest fraction of submicron grains and high density of substructures was also observed. ECAP processing through 4-passes at room temperature experienced a significant increase in both hardness and tensile strength up to 180% and 124%, respectively.

scholarly journals Single-electron detection utilizing coupled nonlinear microresonators

2020 ◽  
Vol 6 (1) ◽  
Author(s):  
Xuefeng Wang ◽  
Xueyong Wei ◽  
Dong Pu ◽  
Ronghua Huan
Keyword(s):  
Scientific Community ◽  
Room Temperature ◽  
Detection Method ◽  
Single Electron ◽  
Nonlinear Coupling ◽  
Electron Charge ◽  
Micromechanical Resonators ◽  
Charge Detection ◽  
Simple Strategy ◽  
Electron Detection

Abstract Since the discovery of the electron, the accurate detection of electrical charges has been a dream of the scientific community. Owing to some remarkable advantages, micro/nanoelectromechanical system-based resonators have been used to design electrometers with excellent sensitivity and resolution. Here, we demonstrate a novel ultrasensitive charge detection method utilizing nonlinear coupling in two micromechanical resonators. We achieve single-electron charge detection with a high resolution up to 0.197 ± 0.056 $${\mathrm{e}}/\sqrt {{\mathrm{Hz}}}$$ e / Hz at room temperature. Our findings provide a simple strategy for measuring electron charges with extreme accuracy.

RECENT DEVELOPMENTS ON 3D INTEGRATION OF METALLIC SET ONTO CMOS PROCESS FOR MEMORY APPLICATION

2012 ◽  
Vol 11 (04) ◽  
pp. 1240024 ◽  
Author(s):  
N. JOUVET ◽  
M. A. BOUNOUAR ◽  
S. ECOFFEY ◽  
C. NAUENHEIM ◽  
A. BEAUMONT ◽  
...  
Keyword(s):  
Room Temperature ◽  
Memory Cell ◽  
Atomic Layer ◽  
Cmos Process ◽  
3D Integration ◽  
Simulation Tools ◽  
Layer Deposition ◽  
Recent Developments ◽  
Sram Memory ◽  
Electrical Characterizations

This work presents a nanodamascene process for a CMOS back-end-of-line fabrication of metallic single electron transistor(SET), together with the use of simulation tools for the development of a SET SRAM memory cell. We show room temperature electrical characterizations of SETs fabricated on CMOS with relaxed dimensions, and simulations of a SET SRAM memory cell. Using their physical characteristics achievable through the use of atomic layer deposition, it will be demonstrated that it has the potential to operate at temperature up to 398 K, and that power consumption is less than that of equivalent circuit in advanced CMOS technologies. In order to take advantage of both low power SETs and high CMOS drive efficiency, a hybrid 3D SET CMOS circuit is proposed.

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