Optimized Crosstalk Circuit for Long Wire Copper Interconnects using 45nm CMOS Inverter

Author(s):  
Himani Bhardwaj ◽  
Sunil Jadav ◽  
Harsh Sohal ◽  
Shruti Jain
2018 ◽  
Author(s):  
Suresh Natarajan ◽  
Cara-Lena Nies ◽  
Michael Nolan

<div>As the critical dimensions of transistors continue to be scaled down to facilitate improved performance and device speeds, new ultrathin materials that combine diffusion barrier and seed/liner properties are needed for copper interconnects at these length scales. Ideally, to facilitate coating of high aspect ratio structures, this alternative barrier+liner material should only consist of one or as few layers as possible. We studied TaN, the current industry standard for Cu diffusion barriers, and Ru, which is a</div><div>suitable liner material for Cu electroplating, to explore how combining these two materials in a barrier+liner material influences the adsorption of Cu atoms in the early stage of Cu film growth. To this end, we carried out first-principles simulations of the adsorption and diffusion of Cu adatoms at Ru-passivated and Ru-doped e-TaN(1 1 0) surfaces. For comparison, we also studied the behaviour of Cu and Ru adatoms at the low index surfaces of e-TaN, as well as the interaction of Cu adatoms with the (0 0 1) surface of hexagonal Ru. Our results confirm the barrier and liner properties of TaN and Ru, respectively while also highlighting the weaknesses of both materials. Ru passivated TaN was found to have improved binding with Cu adatoms as compared to the bare TaN and Ru surfaces.</div><div>On the other hand, the energetic barrier for Cu diffusion at Ru passivated TaN surface was lower than at the bare TaN surface which can promote Cu agglomeration. For Ru-doped TaN however, a decrease in Cu binding energy was found in addition to favourable migration of the Cu adatoms toward the doped Ru atom and unfavourable migration away from it or into the bulk. This suggests that Ru doping sites in the TaN surface can act as nucleation points for Cu growth with high migration barrier preventing agglomeration and allow electroplating of Cu. Therefore Ru-doped TaN is proposed as a candidate for a combined barrier+liner material with reduced thickness.</div>


Author(s):  
Huixian Wu ◽  
James Cargo ◽  
Huixian Wu ◽  
Marvin White

Abstract The integration of copper interconnects and low-K dielectrics will present novel failure modes and reliability issues to failure analysts. This paper discusses failure modes related to Cu/low-K technology. Here, physical failure analysis (FA) techniques including deprocessing and cross-section analysis have been developed. The deprocessing techniques include wet chemical etching, reactive ion etching, chemical mechanical polishing and a combination of these techniques. Case studies on different failure modes related to Cu/low k technology are discussed: copper voiding, copper extrusion; electromigration stress failure; dielectric cracks; delamination-interface adhesion; and FA on circuit-under-pad. For the cross-section analysis of copper/low-K samples, focused ion beam techniques have been developed. Scanning electron microscopy, EDX, and TEM analytical analysis have been used for failure analysis for Cu/low-K technology. Various failure modes and reliability issues have also been addressed.


Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.


2021 ◽  
pp. 2001212
Author(s):  
Tien Dat Ngo ◽  
Zheng Yang ◽  
Myeongjin Lee ◽  
Fida Ali ◽  
Inyong Moon ◽  
...  

2006 ◽  
Vol 504 (1-2) ◽  
pp. 321-324 ◽  
Author(s):  
Young-Bae Park ◽  
Reiner Mönig ◽  
Cynthia A. Volkert

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