Comparison Of Error Detection Techniques Using Software-based Fault Injection

2005 ◽  
Author(s):  
D. Wilson ◽  
G. Sullivan ◽  
G. Masson ◽  
J. Bright
Keyword(s):  
Error Detection ◽  
Fault Injection ◽  
Detection Techniques

Designing and Validation of Error Detection Software

1998 ◽  
Vol 05 (04) ◽  
pp. 337-357
Author(s):  
Sean. J. Geoghegan ◽  
D. R. Avresky
Keyword(s):  
Error Detection ◽  
Fault Injection ◽  
Fault Coverage ◽  
Detection Techniques ◽  
Different Types ◽  
Current Program ◽  
Program Flow ◽  
Detection Software ◽  
Hardware Faults ◽  
Future Program

We propose a systematic approach for design and validation of error detection software. Formally, the semantic of a specification is represented by a transition system. This representation is then used to generate a flowgraph or ddgraph which is used to construct an execution path tree. The information obtained from this algorithm representation is used to aid in the design of software-based fault detection techniques for hardware faults. Flowgraph and ddgraph representations provide information to predict future program flow. During execution, the current program path is recorded, along with the expected path. Checks are placed to verify that the program path follows the predicted path. Algorithm-based fault tolerance (ABFT) techniques are used to detect data structure corrupting faults and to improve the fault coverage. Fault coverage provided by this approach for different types of hardware faults has been estimated through experiments with the software-based fault injection tool (SOFIT) and the data is presented to demonstrate the effectiveness of the method.

A Flexible Fault Injection Platform for the Analysis of the Symptoms of Soft Errors in FPGA Soft Processors

2017 ◽  
Vol 26 (08) ◽  
pp. 1740009
Author(s):  
Aitzan Sari ◽  
Mihalis Psarakis
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Low Cost ◽  
Soft Errors ◽  
Soft Error ◽  
Detection Scheme ◽  
Detection Techniques ◽  
Error Sensitivity ◽  
Depth Analysis

Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in the FPGA configuration memory. To this end, we present a flexible fault injection platform based on an open-source CAD framework (RapidSmith) for the soft error sensitivity analysis of soft processors in Xilinx SRAM-based FPGAs. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. The fault injection is performed on-chip by a dedicated microcontroller which also monitors processor behavior to identify specific symptoms as consequences of soft errors. The performed analysis showed that these symptoms can be used to build an efficient, low-cost error detection scheme. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor.

Real-time error detection techniques based on FPGA

2013 ◽  
Vol 33 (5) ◽  
pp. 1459-1462
Author(s):  
Xiaoming JU ◽  
Jiehao ZHANG ◽  
Yizhong ZHANG
Keyword(s):  
Real Time ◽  
Error Detection ◽  
Time Error ◽  
Detection Techniques

scholarly journals Semi-Automatic Locating of Cryptographic Operations in Side-Channel Traces

2021 ◽  
pp. 345-366
Author(s):  
Jens Trautmann ◽  
Arthur Beckers ◽  
Lennert Wouters ◽  
Stefan Wildermann ◽  
Ingrid Verbauwhede ◽  
...  
Keyword(s):  
Fault Injection ◽  
Side Channel ◽  
Leakage Detection ◽  
Clock Frequency ◽  
Detection Techniques ◽  
Effective Time ◽  
Meta Information ◽  
Software Implementations ◽  
Single Data ◽  
The Time Domain

Locating a cryptographic operation in a side-channel trace, i.e. finding out where it is in the time domain, without having a template, can be a tedious task even for unprotected implementations. The sheer amount of data can be overwhelming. In a simple call to OpenSSL for AES-128 ECB encryption of a single data block, only 0.00028% of the trace relate to the actual AES-128 encryption. The rest is overhead. We introduce the (to our best knowledge) first method to locate a cryptographic operation in a side-channel trace in a largely automated fashion. The method exploits meta information about the cryptographic operation and requires an estimate of its implementation’s execution time.The method lends itself to parallelization and our implementation in a tool greatly benefits from GPU acceleration. The tool can be used offline for trace segmentation and for generating a template which can then be used online in real-time waveformmatching based triggering systems for trace acquisition or fault injection. We evaluate it in six scenarios involving hardware and software implementations of different cryptographic operations executed on diverse platforms. Two of these scenarios cover realistic protocol level use-cases and demonstrate the real-world applicability of our tool in scenarios where classical leakage-detection techniques would not work. The results highlight the usefulness of the tool because it reliably and efficiently automates the task and therefore frees up time of the analyst.The method does not work on traces of implementations protected by effective time randomization countermeasures, e.g. random delays and unstable clock frequency, but is not affected by masking, shuffling and similar countermeasures.

scholarly journals Lookup Table Algorithm for Error Correction in Color Images

2018 ◽  
Vol 2 (2) ◽  
pp. 63
Author(s):  
Ruaa Alaadeen Abdulsattar ◽  
Nada Hussein M. Ali
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
Color Image ◽  
Color Images ◽  
Lookup Table ◽  
Hamming Code ◽  
Detection Techniques ◽  
Error Ratio ◽  
Error Detection And Correction ◽  
Large Burst

Error correction and error detection techniques are often used in wireless transmission systems. A color image of type BMP is considered as an application of developed lookup table algorithms to detect and correct errors in these images. Decimal Matrix Code (DMC) and Hamming code (HC) techniques were integrated to compose Hybrid Matrix Code (HMC) to maximize the error detection and correction. The results obtained from HMC still have some error not corrected because the redundant bits added by Hamming codes to the data are considered inadequate, and it is suitable when the error rate is low for detection and correction processes. Besides, a Hamming code could not detect large burst error period, in addition, the have same values sometimes which lead to not detect the error and consequently increase the error ratio. The proposed algorithm LUT_CORR is presented to detect and correct errors in color images over noisy channels, the proposed algorithm depends on the parallel Cyclic Redundancy Code (CRC) method that's based on two algorithms: Sarwate and slicing By N algorithms. The LUT-CORR and the aforementioned algorithms were merged to correct errors in color images, the output results correct the corrupted images with a 100 % ratio almost. The above high correction ratio due to some unique values that the LUT-CORR algorithm have. The HMC and the proposed algorithm applied to different BMP images, the obtained results from LUT-CORR are compared to HMC for both Mean Square Error (MSE) and correction ratio.  The outcome from the proposed algorithm shows a good performance and has a high correction ratio to retrieve the source BMP image.

A Recovery-Oriented Approach for Software Fault Diagnosis in Complex Critical Systems

2012 ◽  
pp. 29-56
Author(s):  
Gabriella Carrozza ◽  
Roberto Natella
Keyword(s):  
Error Detection ◽  
Traffic Control ◽  
Fault Location ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Critical Systems ◽  
Software Faults ◽  
Real World Application ◽  
Complex Fault ◽  
Detection Quality

This paper proposes an approach to software faults diagnosis in complex fault tolerant systems, encompassing the phases of error detection, fault location, and system recovery. Errors are detected in the first phase, exploiting the operating system support. Faults are identified during the location phase, through a machine learning based approach. Then, the best recovery action is triggered once the fault is located. Feedback actions are also used during the location phase to improve detection quality over time. A real world application from the Air Traffic Control field has been used as case study for evaluating the proposed approach. Experimental results, achieved by means of fault injection, show that the diagnosis engine is able to diagnose faults with high accuracy and at a low overhead.

A Recovery-Oriented Approach for Software Fault Diagnosis in Complex Critical Systems

2011 ◽  
Vol 2 (1) ◽  
pp. 77-104 ◽  
Author(s):  
Gabriella Carrozza ◽  
Roberto Natella
Keyword(s):  
Error Detection ◽  
Traffic Control ◽  
Fault Location ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Critical Systems ◽  
Software Faults ◽  
Real World Application ◽  
Complex Fault ◽  
Detection Quality

This paper proposes an approach to software faults diagnosis in complex fault tolerant systems, encompassing the phases of error detection, fault location, and system recovery. Errors are detected in the first phase, exploiting the operating system support. Faults are identified during the location phase, through a machine learning based approach. Then, the best recovery action is triggered once the fault is located. Feedback actions are also used during the location phase to improve detection quality over time. A real world application from the Air Traffic Control field has been used as case study for evaluating the proposed approach. Experimental results, achieved by means of fault injection, show that the diagnosis engine is able to diagnose faults with high accuracy and at a low overhead.

scholarly journals Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2074
Author(s):  
J.-Carlos Baraza-Calvo ◽  
Joaquín Gracia-Morán ◽  
Luis-J. Saiz-Adalid ◽  
Daniel Gil-Tomás ◽  
Pedro-J. Gil-Vicente
Keyword(s):  
Fault Tolerance ◽  
Error Correction ◽  
Error Detection ◽  
Fault Injection ◽  
Error Correction Codes ◽  
Transient Faults ◽  
Tolerance Mechanism ◽  
Intermittent Faults ◽  
Risc Processor ◽  
Simulation Based

Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction–double error detection (SEC–DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.

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