Effect of Temperature Jump on Nonequilibrium Entropy Generation in a MOSFET Transistor Using Dual-Phase-Lagging Model

2017 ◽  
Vol 139 (12) ◽  
Author(s):  
Fraj Echouchene ◽  
Hafedh Belmabrouk
Keyword(s):  
Boundary Condition ◽  
Entropy Production ◽  
Entropy Generation ◽  
Temperature Jump ◽  
Oxide Semiconductor ◽  
Effect Of Temperature ◽  
Dual Phase ◽  
Conduction Model ◽  
Nonequilibrium Entropy ◽  
Effect Transistor

This paper investigates the effect of temperature-jump boundary condition on nonequilibrium entropy production under the effect of the dual-phase-lagging (DPL) heat conduction model in a two-dimensional sub-100 nm metal-oxide-semiconductor field effect transistor (MOSFET). The transient DPL model is solved using finite element method. Also, the influences of the governing parameters on global entropy generation for the following cases—(I) constant applied temperature, (II) temperature-jump boundary condition, and (III) a realistic MOSFET with volumetric heat source and adiabatic boundaries—are discussed in detail and depicted graphically. The analysis of our results indicates that entropy generation minimization within a MOSFET can be achieved by using temperature-jump boundary condition and for low values of Knudsen number. A significant reduction of the order of 85% of total entropy production is observed when a temperature-jump boundary condition is adopted.

Nonequilibrium Entropy Production Under the Effect of the Dual-Phase-Lag Heat Conduction Model

2000 ◽  
Vol 122 (2) ◽  
pp. 217-223 ◽  
Author(s):  
M. A. Al-Nimr ◽  
M. Naji ◽  
V. S. Arbaci
Keyword(s):  
Heat Conduction ◽  
Entropy Production ◽  
Second Law ◽  
Phase Lag ◽  
Dual Phase ◽  
Conduction Model ◽  
Heat Conduction Model ◽  
Nonequilibrium Entropy ◽  
Phase Lags ◽  
The Difference

In the present work, the nonequilibrium entropy production under the effect of the dual-phase-lag heat conduction model is investigated. It is shown that the entropy production cannot be described using the classical form of the equilibrium entropy production where using this form leads to a violation for the thermodynamics second law. The effect of the phase-lags in temperature and in heat flux on the nonequilibrium entropy production is investigated. Also, the difference between the equilibrium and the nonequilibrium temperatures under the effect of the dual-phase-lag heat conduction model is studied. [S0022-1481(00)01502-4]

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

scholarly journals Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization

Materials ◽  
2021 ◽  
Vol 14 (9) ◽  
pp. 2316
Author(s):  
Kalparupa Mukherjee ◽  
Carlo De Santi ◽  
Matteo Borga ◽  
Karen Geens ◽  
Shuzhen You ◽  
...  
Keyword(s):  
Field Effect Transistor ◽  
Dynamic Performance ◽  
Power Conversion ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Current Analysis ◽  
Power Transistors ◽  
Trench Structure ◽  
Effect Transistor ◽  
Gan On Si

The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considered to design vertical GaN-on-Si stacks with high breakdown voltage. Next, we describe gate design techniques to improve breakdown performance, through variation of dielectric composition coupled with optimization of the trench structure. Finally, we describe how to identify and compare trapping effects with the help of pulsed techniques, combined with light-assisted de-trapping analyses, in order to assess the dynamic performance of the devices.

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